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ADC1610S_SER 4 © IDT 2012. All rights reserved.
Product data sheet Rev. 04 — 2 July 2012 10 of 38
Integrated Device Technology
ADC1610S series
Single 16-bit ADC; CMOS or LVDS DDR digital output
[1] Typical values measured at V
DDA
=3V, V
DDO
=1.8V, T
amb
=25C and C
L
= 5 pF; minimum and maximum values are across the full temperature range T
amb
= 40 C to +85 C
at V
DDA
=3V, V
DDO
= 1.8 V; V
INP
V
INM
= 1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified.
10.2 Clock and digital output timing
IMD intermodulation
distortion
f
i
= 3 MHz - 89 - - 89 - - 88 - - 89 - dBc
f
i
=30MHz - 88-- 88--88--88-dBc
f
i
=70MHz - 87-- 87--86--86-dBc
f
i
= 170 MHz - 84 - - 85 - - 83 - - 84 - dBc
Table 7. Dynamic characteristics …continued
Symbol Parameter Conditions ADC1610S065 ADC1610S080 ADC1610S105 ADC1610S125 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Table 8. Clock and digital output timing characteristics
[1]
Symbol Parameter Conditions ADC1610S065 ADC1610S080 ADC1610S105 ADC1610S125 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Clock timing input: pins CLKP and CLKM
f
clk
clock
frequency
40 - 65 60 - 80 75 - 105 100 - 125 MHz
t
lat(data)
data latency
time
-13.5--13.5--13.5--13.5-clock
cycles
clk
clock duty
cycle
DCS_EN = logic 1 30 50 70 30 50 70 30 50 70 30 50 70 %
DCS_EN = logic 0 45 50 55 45 50 55 45 50 55 45 50 55 %
t
d(s)
sampling
delay time
-0.8--0.8--0.8--0.8-ns
t
wake
wake-up time -76--76--76--76-s
CMOS Mode timing output: pins D15 to D0 and DAV
t
PD
propagation
delay
DATA 13.6 14.9 16.4 11.9 12.9 14.4 8.0 10.8 12.4 8.2 9.7 11.3 ns
DAV -4.2--3.6--3.3--3.4-ns
t
su
set-up time - 12.5 - - 9.8 - - 6.8 - - 5.6 - ns
t
h
hold time - 3.4 - - 3.3 - - 3.1 - - 2.8 - ns
t
r
rise time DATA
[2]
0.39 - 2.4 0.39 - 2.4 0.39 - 2.4 0.39 - 2.4 ns
DAV 0.26 - 2.4 0.26 - 2.4 0.26 - 2.4 0.26 - 2.4 ns
t
f
fall time DATA
[2]
0.19 - 2.4 0.19 - 2.4 0.19 - 2.4 0.19 - 2.4 ns