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ADC1610S105HN/C1:5

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38
ADC1610S_SER 4 © IDT 2012. All rights reserved.
Product data sheet Rev. 04 — 2 July 2012 25 of 38
Integrated Device Technology
ADC1610S series
Single 16-bit ADC; CMOS or LVDS DDR digital output
The output resistance is 50 and is the combination of an internal resistor and the
equivalent output resistance of the buffer. There is no need for an external damping
resistor. The drive strength of both data and DAV buffers can be programmed via the SPI
in order to adjust the rise and fall times of the output digital signals (see Table 30):
11.5.2 Digital output buffers: LVDS DDR mode
The digital output buffers can be configured as LVDS DDR by setting bit LVDS_CMOS to
logic 1 (see Table 23).
Each output should be terminated externally with a 100 resistor (typical) at the receiver
side (Figure 31) or internally via SPI control bits LVDS_INT_TER[2:0] (see Figure 32 and
Table 32).
The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via
the SPI (bits DAVI[1:0] and DATAI[1:0]; see Table 31) in order to adjust the output logic
voltage levels.
Fig 30. LVDS DDR digital output buffer - externally terminated
Fig 31. LVDS DDR digital output buffer - internally terminated
005aaa123
VDDO
3.5 mA
typ
D
x
P/D
x + 1
P
D
x
M/D
x + 1
M
AGND
100 Ω
−
+
−
+
RECEIVER
100 Ω
005aaa124
VDDO
3.5 mA
typ
D
x
P/D
x + 1
P
D
x
M/D
x + 1
M
AGND
−
+
−
+
RECEIVER
ADC1610S_SER 4 © IDT 2012. All rights reserved.
Product data sheet Rev. 04 — 2 July 2012 26 of 38
Integrated Device Technology
ADC1610S series
Single 16-bit ADC; CMOS or LVDS DDR digital output
11.5.3 DAta Valid (DAV) output clock
A data valid output clock signal (DAV) can be used to capture the data delivered by the
ADC1610S. Detailed timing diagrams for CMOS and LVDS DDR modes are shown in
Figure 4 and Figure 5 respectively.
11.5.4 Out-of-Range (OTR)
An out-of-range signal is provided on pin OTR. The latency of OTR is fourteen clock
cycles. The OTR response can be speeded up by enabling Fast OTR (bit
FASTOTR = logic 1; see Table 29). In this mode, the latency of OTR is reduced to only
four clock cycles. The Fast OTR detection threshold (below full-scale) can be
programmed via bits FASTOTR_DET[2:0].
11.5.5 Digital offset
By default, the ADC1610S delivers output code that corresponds to the analog input.
However it is possible to add a digital offset to the output code via the SPI (bits
DIG_OFFSET[5:0]; see Table 25).
11.5.6 Test patterns
For test purposes, the ADC1610S can be configured to transmit one of a number of
predefined test patterns (via bits TESTPAT_SEL[2:0]; see Table 26). A custom test pattern
can be defined by the user (TESTPAT_USER[15:0]; see Table 27 and Table 28) and is
selected when TESTPAT_SEL[2:0] = 101. The selected test pattern is transmitted
regardless of the analog input.
Table 14. LVDS DDR output register 2
LVDS_INT_TER[1:0] Resistor value ()
000 no internal termination
001 300
010 180
011 110
100 150
101 100
110 81
111 60
Table 15. Fast OTR register
FASTOTR_DET[2:0] Detection level (dB)
000 20.56
001 16.12
010 11.02
011 7.82
100 5.49
101 3.66
110 2.14
111 0.86
ADC1610S_SER 4 © IDT 2012. All rights reserved.
Product data sheet Rev. 04 — 2 July 2012 27 of 38
Integrated Device Technology
ADC1610S series
Single 16-bit ADC; CMOS or LVDS DDR digital output
11.5.7 Output codes versus input voltage
11.6 Serial peripheral interface
11.6.1 Register description
The ADC1610S serial interface is a synchronous serial communications port that allows
easy interfacing with many commonly-used microprocessors. It provides access to the
registers that control the operation of the chip.
This interface is configured as a 3-wire type (SDIO as bidirectional pin)
Pin SCLK is the serial clock input and pin CS
is the chip select pin.
Each read/write operation is initiated by a LOW level on pin CS
. A minimum of three bytes
is transmitted (two instruction bytes and at least one data byte). The number of data bytes
is determined by the value of bits W1 and W2 (see Table 18).
[1] Bit R/W indicates whether it is a read (logic 1) or a write (logic 0) operation.
[2] Bits W1 and W0 indicate the number of bytes to be transferred after the instruction byte (see Table 18).
Table 16. Output codes
V
INP
V
INM
Offset binary Two’s complement OTR pin
< 1 0000 0000 0000 0000 1000 0000 0000 0000 1
1 0000 0000 0000 0000 1000 0000 0000 0000 0
0.99996948 0000 0000 0000 0001 1000 0000 0000 0001 0
0.99993896 0000 0000 0000 0010 1000 0000 0000 0010 0
0.99990845 0000 0000 0000 0011 1000 0000 0000 0011 0
0.99987793 0000 0000 0000 0100 1000 0000 0000 0100 0
.... .... .... 0
0.00006104 0111 1111 1111 1110 1111 1111 1111 1110 0
0.00003052 0111 1111 1111 1111 1111 1111 1111 1111 0
0 1000 0000 0000 0000 0000 0000 0000 0000 0
+0.00003052 1000 0000 0000 0001 0000 0000 0000 0001 0
+0.00006104 1000 0000 0000 0010 0000 0000 0000 0010 0
.... .... .... 0
+0.99987793 1111 1111 1111 1011 0111 1111 1111 1011 0
+0.99990845 1111 1111 1111 1100 0111 1111 1111 1100 0
+0.99993896 1111 1111 1111 1101 0111 1111 1111 1101 0
+0.99996948 1111 1111 1111 1110 0111 1111 1111 1110 0
+1 1111 1111 1111 1111 0111 1111 1111 1111 0
> +1 1111 1111 1111 1111 0111 1111 1111 1111 1
Table 17. Instruction bytes for the SPI
MSB LSB
Bit 76543210
Description R/W
[1]
W1
[2]
W0
[2]
A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38

ADC1610S105HN/C1:5

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