SC16C754B_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 6 October 2008 10 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
6.2 Hardware flow control
Hardware flow control is comprised of auto-CTS and auto-RTS. Auto-CTS and auto-RTS
can be enabled/disabled independently by programming EFR[7:6].
With auto-CTS, CTS must be active before the UART can transmit data.
Auto-RTS only activates the RTS output when there is enough room in the FIFO to receive
data and de-activates the RTS output when the RX FIFO is sufficiently full. The halt and
resume trigger levels in the TCR determine the levels at which RTS is
activated/deactivated.
If both auto-CTS and auto-RTS are enabled, when RTS is connected to CTS, data
transmission does not occur unless the receiver FIFO has empty space. Thus, overrun
errors are eliminated during hardware flow control. If not enabled, overrun errors occur if
the transmit data rate exceeds the receive FIFO servicing latency.
Fig 5. Autoflow control (auto-RTS and auto-CTS) example
RX
FIFO
FLOW
CONTROL
TX
FIFO
PARALLEL
TO SERIAL
TX
FIFO
RX
FIFO
UART 1 UART 2
D7 to D0
RX TX
RTS CTS
TX RX
CTS RTS
D7 to D0
002aaa228
SERIAL TO
PARALLEL
SERIAL TO
PARALLEL
FLOW
CONTROL
FLOW
CONTROL
FLOW
CONTROL
PARALLEL
TO SERIAL
SC16C754B_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 6 October 2008 11 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
6.2.1 Auto-RTS
Auto-RTS data flow control originates in the receiver block (see Figure 1 “Block diagram of
SC16C754B”). Figure 6 shows RTS functional timing. The receiver FIFO trigger levels
used in auto-RTS are stored in the TCR. RTS is active if the RX FIFO level is below the
halt trigger level in TCR[3:0]. When the receiver FIFO halt trigger level is reached, RTS is
de-asserted. The sending device (for example, another UART) may send an additional
byte after the trigger level is reached (assuming the sending UART has another byte to
send) because it may not recognize the de-assertion of RTS until it has begun sending the
additional byte. RTS is automatically reasserted once the receiver FIFO reaches the
resume trigger level programmed via TCR[7:4]. This re-assertion allows the sending
device to resume transmission.
6.2.2 Auto-CTS
The transmitter circuitry checks CTS before sending the next data byte. When CTS is
active, the transmitter sends the next byte. To stop the transmitter from sending the
following byte, CTS must be de-asserted before the middle of the last stop bit that is
currently being sent. The auto-CTS function reduces interrupts to the host system. When
flow control is enabled, CTS level changes do not trigger host interrupts because the
device automatically controls its own transmitter. Without auto-CTS, the transmitter sends
any data present in the transmit FIFO and a receiver overrun error may result.
N = receiver FIFO trigger level.
The two blocks in dashed lines cover the case where an additional byte is sent, as described in Section 6.2.1.
Fig 6. RTS functional timing
Start byte N Start byte N + 1 StartStop StopRX
RTS
IOR
N N+112
002aaa226
When CTS is LOW, the transmitter keeps sending serial data out.
When CTS goes HIGH before the middle of the last stop bit of the current byte, the transmitter
finishes sending the current byte, but it does not send the next byte.
When CTS goes from HIGH to LOW, the transmitter begins sending data again.
Fig 7. CTS functional timing
Start byte 0 to 7 StopTX
CTS
002aaa227
Start byte 0 to 7 Stop
SC16C754B_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 6 October 2008 12 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
6.3 Software flow control
Software flow control is enabled through the enhanced feature register and the modem
control register. Different combinations of software flow control can be enabled by setting
different combinations of EFR[3:0]. Table 3 shows software flow control options.
Remark: When using software flow control, the Xon/Xoff characters cannot be used for
data characters.
There are two other enhanced features relating to software flow control:
‘Xon Any’ function (MCR[5]): Operation will resume after receiving any character
after recognizing the Xoff character. It is possible that an Xon1 character is
recognized as an ‘Xon Any’ character, which could cause an Xon2 character to be
written to the RX FIFO.
Special character (EFR[5]): Incoming data is compared to Xoff2. Detection of the
special character sets the Xoff interrupt (IIR[4]) but does not halt transmission. The
Xoff interrupt is cleared by a read of the IIR. The special character is transferred to the
RX FIFO.
6.3.1 RX
When software flow control operation is enabled, the SC16C754B will compare incoming
data with Xoff1/Xoff2 programmed characters (in certain cases, Xoff1 and Xoff2 must be
received sequentially). When the correct Xoff character is received, transmission is halted
after completing transmission of the current character. Xoff detection also sets IIR[4] (if
enabled via IER[5]) and causes INT to go HIGH.
To resume transmission, an Xon1/Xon2 character must be received (in certain cases
Xon1 and Xon2 must be received sequentially). When the correct Xon characters are
received, IIR[4] is cleared, and the Xoff interrupt disappears.
Table 3. Software flow control options (EFR[3:0])
EFR[3] EFR[2] EFR[1] EFR[0] TX, RX software flow controls
0 0 X X no transmit flow control
1 0 X X transmit Xon1, Xoff1
0 1 X X transmit Xon2, Xoff2
1 1 X X transmit Xon1, Xon2, Xoff1, Xoff2
X X 0 0 no receive flow control
X X 1 0 receiver compares Xon1, Xoff1
X X 0 1 receiver compares Xon2, Xoff2
1 0 1 1 transmit Xon1, Xoff1
receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0 1 1 1 transmit Xon2, Xoff2
receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1 1 1 1 transmit Xon1, Xon2, Xoff1, Xoff2
receiver compares Xon1 and Xon2, Xoff1 and Xoff2
0 0 1 1 no transmit flow control
receiver compares Xon1 and Xon2, Xoff1 and Xoff2

SC16C754BIA68,529

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC 16CB 2.5V-5V 4CH
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union