SC16C754B_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 6 October 2008 28 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
7.7 Modem Status Register (MSR)
This 8-bit register provides information about the current state of the control lines from the
modem, data set, or peripheral device to the processor. It also indicates when a control
input from the modem changes state. Table 15 shows modem status register bit settings
per channel.
[1] The primary inputs RI, CD, CTS, DSR are all active LOW, but their registered equivalents in the MSR and
MCR (in loopback) registers are active HIGH.
Table 15. Modem status register bits description
Bit Symbol Description
7 MSR[7]
[1]
CD (active HIGH, logic 1). This bit is the complement of the CD input during
normal mode. During internal loopback mode, it is equivalent to MCR[3].
6 MSR[6]
[1]
RI (active HIGH, logic 1). This bit is the complement of the RI input during
normal mode. During internal loopback mode, it is equivalent to MCR[2].
5 MSR[5]
[1]
DSR (active HIGH, logic 1). This bit is the complement of the DSR input
during normal mode. During internal loopback mode, it is equivalent MCR[0].
4 MSR[4]
[1]
CTS (active HIGH, logic 1). This bit is the complement of the CTS input
during normal mode. During internal loopback mode, it is equivalent to
MCR[1].
3 MSR[3] CD. Indicates that
CD input (or MCR[3] in loopback mode) has changed
state. Cleared on a read.
2 MSR[2] RI. Indicates that
RI input (or MCR[2] in loopback mode) has changed state
from LOW to HIGH. Cleared on a read.
1 MSR[1] DSR. Indicates that
DSR input (or MCR[0] in loopback mode) has changed
state. Cleared on a read.
0 MSR[0] CTS. Indicates that CTS input (or MCR[1] in loopback mode) has changed
state. Cleared on a read.
SC16C754B_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 6 October 2008 29 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
7.8 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) enables each of the six types of interrupt, receiver
error, RHR interrupt, THR interrupt, Xoff received, or CTS/RTS change of state from LOW
to HIGH. The INT output signal is activated in response to interrupt generation. Table 16
shows the interrupt enable register bit settings.
[1] IER[7:4] can only be modified if EFR[4] is set, that is, EFR[4] is a write enable. Re-enabling IER[1] will
cause a new interrupt if the THR is below the threshold.
Table 16. Interrupt enable register bits description
Bit Symbol Description
7 IER[7]
[1]
CTS interrupt enable.
logic 0 = disable the
CTS interrupt (normal default condition)
logic 1 = enable the
CTS interrupt
6 IER[6]
[1]
RTS interrupt enable.
logic 0 = disable the
RTS interrupt (normal default condition)
logic 1 = enable the
RTS interrupt
5 IER[5]
[1]
Xoff interrupt.
logic 0 = disable the Xoff interrupt (normal default condition)
logic 1 = enable the Xoff interrupt
4 IER[4]
[1]
Sleep mode.
logic 0 = disable Sleep mode (normal default condition)
logic 1 = enable Sleep mode. See
Section 6.7 “Sleep mode” for details.
3 IER[3] Modem status interrupt.
logic 0 = disable the modem status register interrupt (normal default
condition)
logic 1 = enable the modem status register interrupt
2 IER[2] Receive line status interrupt.
logic 0 = disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt
1 IER[1] Transmit holding register interrupt.
logic 0 = disable the THR interrupt (normal default condition)
logic 1 = enable the THR interrupt
0 IER[0] Receive holding register interrupt.
logic 0 = disable the RHR interrupt (normal default condition)
logic 1 = enable the RHR interrupt
SC16C754B_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 6 October 2008 30 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
7.9 Interrupt Identification Register (IIR)
The IIR is a read-only 8-bit register which provides the source of the interrupt in a
prioritized manner. Table 17 shows interrupt identification register bit settings.
The interrupt priority list is shown in Table 18.
Table 17. Interrupt identification register bits description
Bit Symbol Description
7:6 IIR[7:6] Mirror the contents of FCR[0].
5 IIR[5]
RTS/CTS LOW-to-HIGH change of state.
4 IIR[4] 1 = Xoff/special character has been detected.
3:1 IIR[3:1] 3-bit encoded interrupt. See
Table 18.
0 IIR[0] Interrupt status.
logic 0 = an interrupt is pending
logic 1 = no interrupt is pending
Table 18. Interrupt priority list
Priority
level
IIR[5] IIR[4] IIR[3] IIR[2] IIR[1] IIR[0] Source of the interrupt
1 0 0 0 1 1 0 Receiver line status error
2 0 0 1 1 0 0 Receiver time-out interrupt
2 0 0 0 1 0 0 RHR interrupt
3 0 0 0 0 1 0 THR interrupt
4 0 0 0 0 0 0 Modem interrupt
5 0 1 0 0 0 0 Received Xoff signal/
special character
6 100000
CTS, RTS change of state from
active (LOW) to inactive (HIGH)

SC16C754BIA68,529

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC 16CB 2.5V-5V 4CH
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New from this manufacturer.
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