SC16C754B_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 6 October 2008 37 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
11. Dynamic characteristics
Table 26. Dynamic characteristics
T
amb
=
−
40
°
C to +85
°
C; tolerance of V
CC
±
10 %, unless otherwise specified.
Symbol Parameter Conditions V
CC
= 2.5 V V
CC
= 3.3 V V
CC
= 5.0 V Unit
Min Max Min Max Min Max
t
WL
pulse width LOW 10 - 6 - 6 - ns
t
WH
pulse width HIGH 10 - 6 - 6 - ns
f
XTAL
oscillator/clock frequency
[1][2]
-48-80 80MHz
t
6s
address set-up time 0 - 0 - 0 - ns
t
6h
address hold time 0 - 0 - 0 - ns
t
7d
IOR delay from chip select 10 - 10 - 10 - ns
t
7w
IOR strobe width 25 pF load 90 - 26 - 23 - ns
t
7h
chip select hold time from IOR 0-0-0-ns
t
9d
read cycle delay 25 pF load 20 - 20 - 20 - ns
t
12d
delay from IOR to data 25 pF load - 90 - 26 - 23 ns
t
12h
data disable time 25 pF load - 15 - 15 - 15 ns
t
13d
IOW delay from chip select 10 - 10 - 10 - ns
t
13w
IOW strobe width 20 - 20 - 15 - ns
t
13h
chip select hold time from IOW 0-0-0-ns
t
15d
write cycle delay 25 - 25 - 20 - ns
t
16s
data set-up time 20 - 15 - 15 - ns
t
16h
data hold time 15 - 5 - 5 - ns
t
17d
delay from IOW to output 25 pF load - 100 - 33 - 29 ns
t
18d
delay to set interrupt from
Modem input
25 pF load - 100 - 24 - 23 ns
t
19d
delay to reset interrupt from
IOR
25 pF load - 100 - 24 - 23 ns
t
20d
delay from stop to set interrupt - 1T
RCLK
[3]
-1T
RCLK
[3]
-1T
RCLK
[3]
ns
t
21d
delay from IOR to reset
interrupt
25 pF load - 100 - 29 - 28 ns
t
22d
delay from start to set interrupt - 100 - 45 - 40 ns
t
23d
delay from IOW to transmit start 8T
RCLK
[3]
24T
RCLK
[3]
8T
RCLK
[3]
24T
RCLK
[3]
8T
RCLK
[3]
24T
RCLK
[3]
ns
t
24d
delay from IOW to reset
interrupt
-100-45-40ns
t
25d
delay from stop to set RXRDY-1T
RCLK
[3]
-1T
RCLK
[3]
-1T
RCLK
[3]
ns
t
26d
delay from IOR to reset RXRDY -100-45-40ns
t
27d
delay from IOW to set TXRDY -100-45-40ns
t
28d
delay from start to reset TXRDY-8T
RCLK
[3]
-8T
RCLK
[3]
-8T
RCLK
[3]
ns
t
RESET
RESET pulse width
[4]
200 - 200 - 200 - ns
N baud rate divisor 1 (2
16
− 1) 1 (2
16
− 1) 1 (2
16
− 1)
