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SC16C754BIA68,529

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51
SC16C754B_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 6 October 2008 19 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
6.8 Break and time-out conditions
An RX idle condition is detected when the receiver line, RX, has been HIGH for
4 character time. The receiver line is sampled midway through each bit.
When a break condition occurs, the TX line is pulled LOW. A break condition is activated
by setting LCR[6].
6.9 Programmable baud rate generator
The SC16C754B UART contains a programmable baud generator that takes any clock
input and divides it by a divisor in the range between 1 and (2
16
− 1). An additional
divide-by-4 prescaler is also available and can be selected by MCR[7], as shown in
Figure 13. The output frequency of the baud rate generator is 16 × the baud rate. The
formula for the divisor is given in Equation 1:
(1)
Where:
prescaler = 1, when MCR[7] is set to 0 after reset (divide-by-1 clock selected)
prescaler = 4, when MCR[7] is set to 1 after reset (divide-by-4 clock selected).
Remark: The default value of prescaler after reset is divide-by-1.
Figure 13 shows the internal prescaler and baud rate generator circuitry.
DLL and DLM must be written to in order to program the baud rate. DLL and DLM are the
least significant and most significant byte of the baud rate divisor. If DLL and DLM are
both zero, the UART is effectively disabled, as no baud clock will be generated.
Remark: The programmable baud rate generator is provided to select both the transmit
and receive clock rates.
Table 7 and Table 8 show the baud rate and divisor correlation for crystal with frequency
1.8432 MHz and 3.072 MHz, respectively.
Figure 14 shows the crystal clock circuit reference.
Fig 13. Prescaler and baud rate generator block diagram
divisor
XTAL1 crystal input frequency
prescaler
-------------------------------------------------------------------------------------


desired baud rate 16×()
------------------------------------------------------------------------------------------
=
BAUD RATE
GENERATOR
LOGIC
MCR[7] = 1
MCR[7] = 0
PRESCALER
LOGIC
(DIVIDE-BY-1)
INTERNAL
OSCILLATOR
LOGIC
002aaa233
XTAL1
XTAL2
input clock
PRESCALER
LOGIC
(DIVIDE-BY-4)
reference
clock
internal
baud rate
clock for
transmitter
and receiver
SC16C754B_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 6 October 2008 20 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Table 7. Baud rates using a 1.8432 MHz crystal
Desired baud rate Divisor used to generate
16× clock
Percent error difference
between desired and actual
50 2304
75 1536
110 1047 0.026
134.5 857 0.058
150 768
300 384
600 192
1200 96
1800 64
2000 58 0.69
2400 48
3600 32
4800 24
7200 16
9600 12
19200 6
38400 3
56000 2 2.86
Table 8. Baud rates using a 3.072 MHz crystal
Desired baud rate Divisor used to generate
16× clock
Percent error difference
between desired and actual
50 3840
75 2560
110 1745 0.026
134.5 1428 0.034
150 1280
300 640
600 320
1200 160
1800 107 0.312
2000 96
2400 80
3600 53 0.628
4800 40
7200 27 1.23
9600 20
19200 10
38400 5
SC16C754B_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 6 October 2008 21 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
7. Register descriptions
Each register is selected using address lines A0, A1, A2, and in some cases, bits from
other registers. The programming combinations for register selection are shown in
Table 9.
[1] MCR[7] can only be modified when EFR[4] is set.
[2] Accessed by a combination of address pins and register bits.
[3] Accessible only when LCR[7] is logic 1.
[4] Accessible only when LCR is set to 1011 1111 (BFh).
[5] Accessible only when EFR[4] = 1 and MCR[6] = 1, that is, EFR[4] and MCR[6] are read/write enables.
[6] Accessible only when CSA to CSD = 0, MCR[2] = 1, and loopback is disabled (MCR[4] = 0).
Fig 14. Crystal oscillator connection
002aaa870
C2
47 pF
XTAL1 XTAL2
X1
1.8432 MHz
C1
22 pF
C2
33 pF
XTAL1 XTAL2
1.5 kΩ
X1
1.8432 MHz
C1
22 pF
Table 9. Register map - read/write properties
A2 A1 A0 Read mode Write mode
0 0 0 Receive Holding Register (RHR) Transmit Holding Register (THR)
0 0 1 Interrupt Enable Register (IER) Interrupt Enable Register (IER)
0 1 0 Interrupt Identification Register (IIR) FIFO Control Register (FCR)
0 1 1 Line Control Register (LCR) Line Control Register (LCR)
1 0 0 Modem Control Register (MCR)
[1]
Modem Control Register (MCR)
[1]
1 0 1 Line Status Register (LSR) not applicable
1 1 0 Modem Status Register (MSR) not applicable
1 1 1 ScratchPad Register (SPR) ScratchPad Register (SPR)
0 0 0 Divisor Latch LSB (DLL)
[2][3]
Divisor Latch LSB (DLL)
[2][3]
0 0 1 Divisor Latch MSB (DLM)
[2][3]
Divisor Latch MSB (DLM)
[2][3]
0 1 0 Enhanced Feature Register (EFR)
[2][4]
Enhanced Feature Register (EFR)
[2][4]
1 0 0 Xon1 word
[2][4]
Xon1 word
[2][4]
1 0 1 Xon2 word
[2][4]
Xon2 word
[2][4]
1 1 0 Xoff1 word
[2][4]
Xoff1 word
[2][4]
1 1 1 Xoff2 word
[2][4]
Xoff2 word
[2][4]
1 1 0 Transmission Control Register
(TCR)
[2][5]
Transmission Control Register
(TCR)
[2][5]
1 1 1 Trigger Level Register (TLR)
[2][5]
Trigger Level Register (TLR)
[2][5]
1 1 1 FIFO ready register
[2][6]
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SC16C754BIA68,529

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Manufacturer:
NXP Semiconductors
Description:
UART Interface IC 16CB 2.5V-5V 4CH
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