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SC16C754BIA68,529

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51
SC16C754B_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 6 October 2008 7 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
CSA 7 9 16 I Chip Select (active LOW). These pins enable data transfers between
the user CPU and the SC16C754B for the channel(s) addressed.
Individual UART sections (A, B, C, D) are addressed by providing a logic
LOW on the respective
CSA through CSD pins.
CSB 11 13 20
CSC 38 49 50
CSD 42 53 54
CTSA 2 4 11 I Clear to Send (active LOW). These inputs are associated with individual
UART channels A through D. A logic 0 (LOW) on the
CTS pins indicates
the modem or data set is ready to accept transmit data from the
SC16C754B. Status can be tested by reading MSR[4]. These pins only
affect the transmit and receive operations when auto-
CTS function is
enabled via the Enhanced Feature Register EFR[7] for hardware flow
control operation.
CTSB 16 18 25
CTSC 33 44 45
CTSD 47 58 59
D0 to D7 53, 54,
55, 56,
57, 58,
59, 60
68, 69,
70, 71,
72, 73,
74, 75
66, 67,
68, 1, 2,
3, 4, 5
I/O Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for
transferring information to or from the controlling CPU. D0 is the least
significant bit and the first data bit in a transmit or receive serial data
stream.
DSRA 1 3 10 I Data Set Ready (active LOW). These inputs are associated with
individual UART channels A through D. A logic 0 (LOW) on these pins
indicates the modem or data set is powered-on and is ready for data
exchange with the UART. The state of these inputs is reflected in the
Modem Status Register (MSR).
DSRB 17 19 26
DSRC 32 43 44
DSRD 48 59 60
DTRA 3 5 12 O Data Terminal Ready (active LOW). These outputs are associated with
individual UART channels A through D. A logic 0 (LOW) on these pins
indicates that the SC16C754B is powered-on and ready. These pins can
be controlled via the Modem Control Register (MCR). Writing a logic 1 to
MCR[0] will set the
DTR output to logic 0 (LOW), enabling the modem.
The output of these pins will be a logic 1 after writing a logic 0 to MCR[0],
or after a reset.
DTRB 15 17 24
DTRC 34 45 46
DTRD 46 57 58
GND 14, 28,
45, 61
16, 36,
56, 76
6, 23,
40, 57
I Signal and power ground.
INTA 6 8 15 O Interrupt A, B, C, and D (active HIGH). These pins provide individual
channel interrupts INTA through INTD. INTA through INTD are enabled
when MCR[3] is set to a logic 1, interrupt sources are enabled in the
Interrupt Enable Register (IER). Interrupt conditions include: receiver
errors, available receiver buffer data, available transmit buffer space, or
when a modem status flag is detected. INTA to INTD are in the
high-impedance state after reset.
INTB 12 14 21
INTC 37 48 49
INTD 43 54 55
INTSEL - 67 65 I Interrupt Select (active HIGH with internal pull-down). INTSEL can be
used in conjunction with MCR[3] to enable or disable the 3-state
interrupts INTA to INTD or override MCR[3] and force continuous
interrupts. Interrupt outputs are enabled continuously by making this pin a
logic 1. Driving this pin LOW allows MCR[3] to control the 3-state
interrupt output. In this mode, MCR[3] is set to a logic 1 to enable the
3-state outputs. This pin is associated with LQFP80 and PLCC68
packages only. This pin is connected to GND internally on the LQFP64
package.
IOR 40 51 52 I Input/Output Read strobe (active LOW). A HIGH-to-LOW transition on
IOR will load the contents of an internal register defined by address bits
A[2:0] onto the SC16C754B data bus (D[7:0]) for access by external
CPU.
Table 2. Pin description
…continued
Symbol Pin Type Description
LQFP64 LQFP80 PLCC68
SC16C754B_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 6 October 2008 8 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
IOW 9 11 18 I Input/Output Write strobe (active LOW). A LOW-to-HIGH transition on
IOW will transfer the contents of the data bus (D[7:0]) from the external
CPU to an internal register that is defined by address bits A[2:0] and
CSA
and
CSD.
n.c. - 1, 2, 20,
21, 22,
27, 40,
41, 42,
60, 61,
62, 80
31 - not connected
RESET 27 33 37 I Reset. This pin will reset the internal registers and all the outputs. The
UART transmitter output and the receiver input will be disabled during
reset time. RESET is an active HIGH input.
RIA 63 78 8 I Ring Indicator (active LOW). These inputs are associated with
individual UART channels, A through D. A logic 0 on these pins indicates
the modem has received a ringing signal from the telephone line. A
LOW-to-HIGH transition on these input pins generates a modem status
interrupt, if enabled. The state of these inputs is reflected in the Modem
Status Register (MSR).
RIB 19 24 28
RIC 30 38 42
RID 50 64 62
RTSA 5 7 14 O Request to Send (active LOW). These outputs are associated with
individual UART channels, A through D. A logic 0 on the
RTS pin
indicates the transmitter has data ready and waiting to send. Writing a
logic 1 in the Modem Control Register MCR[1] will set this pin to a logic 0,
indicating data is available. After a reset these pins are set to a logic 1.
These pins only affect the transmit and receive operations when
auto-
RTS function is enabled via the Enhanced Feature Register
(EFR[6]) for hardware flow control operation.
RTSB 13 15 22
RTSC 36 47 48
RTSD 44 55 56
RXA 62 77 7 I Receive data input. These inputs are associated with individual serial
channel data to the SC16C754B. During the local loopback mode, these
RX input pins are disabled and TX data is connected to the UART RX
input internally.
RXB 20 25 29
RXC 29 37 41
RXD 51 65 63
RXRDY - 34 38 O Receive Ready (active LOW). RXRDY contains the wire-ORed status of
all four receive channel FIFOs, RXRDYA to RXRDY D. It goes LOW
when the trigger level has been reached or a time-out interrupt occurs. It
goes HIGH when all RX FIFOs are empty and there is an error in RX
FIFO. This pin is associated with LQFP80 and PLCC68 packages only.
TXA8 1017OTransmit data. These outputs are associated with individual serial
transmit channel data from the SC16C754B. During the local loopback
mode, the TX output pin is disabled and TX data is internally connected
to the UART RX input.
TXB 10 12 19
TXC 39 50 51
TXD 41 52 53
TXRDY - 35 39 O Transmit Ready (active LOW). TXRDY contains the wire-ORed status of
all four transmit channel FIFOs, TXRDYA to TXRDY D. It goes LOW
when there are a trigger level number of spaces available. It goes HIGH
when all four TX buffers are full. This pin is associated with LQFP80 and
PLCC68 packages only.
Table 2. Pin description
…continued
Symbol Pin Type Description
LQFP64 LQFP80 PLCC68
SC16C754B_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 6 October 2008 9 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
6. Functional description
The SC16C754B UART is pin-compatible with the SC16C554 and SC16C654 UARTs. It
provides more enhanced features. All additional features are provided through a special
enhanced feature register.
The UART will perform serial-to-parallel conversion on data characters received from
peripheral devices or modems, and parallel-to-parallel conversion on data characters
transmitted by the processor. The complete status of each channel of the SC16C754B
UART can be read at any time during functional operation by the processor.
The SC16C754B can be placed in an alternate mode (FIFO mode) relieving the processor
of excessive software overhead by buffering received/transmitted characters. Both the
receiver and transmitter FIFOs can store up to 64 bytes (including three additional bits of
error status per byte for the receiver FIFO) and have selectable or programmable trigger
levels. Primary outputs RXRDY and TXRDY allow signalling of DMA transfers.
The SC16C754B has selectable hardware flow control and software flow control.
Hardware flow control significantly reduces software overhead and increases system
efficiency by automatically controlling serial data flow using the RTS output and CTS input
signals. Software flow control automatically controls data flow by using programmable
Xon/Xoff characters.
The UART includes a programmable baud rate generator that can divide the timing
reference clock input by a divisor between 1 and (2
16
− 1).
6.1 Trigger levels
The SC16C754B provides independent selectable and programmable trigger levels for
both receiver and transmitter DMA and interrupt generation. After reset, both transmitter
and receiver FIFOs are disabled and so, in effect, the trigger level is the default value of
one byte. The selectable trigger levels are available via the FIFO Control Register (FCR).
The programmable trigger levels are available via the Trigger Level Register (TLR).
V
CC
4, 21,
35, 52
6, 46, 66 13, 47,
64
I Power supply input.
XTAL1 25 31 35 I Crystal or external clock input. Functions as a crystal input or as an
external clock input. A crystal can be connected between XTAL1 and
XTAL2 to form an internal oscillator circuit (see
Figure 14). Alternatively,
an external clock can be connected to this pin to provide custom data
rates.
XTAL2 26 32 36 O Output of the crystal oscillator or buffered clock (see also XTAL1).
XTAL2 is used as a crystal oscillator output or a buffered clock output.
Table 2. Pin description
…continued
Symbol Pin Type Description
LQFP64 LQFP80 PLCC68
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51

SC16C754BIA68,529

Mfr. #:
Buy SC16C754BIA68,529
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC 16CB 2.5V-5V 4CH
Lifecycle:
New from this manufacturer.
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