SC16C754B_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 6 October 2008 6 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
5.2 Pin description
Fig 4. Pin configuration for PLCC68
SC16C754BIA68
DSRA DSRD
CTSA CTSD
DTRA DTRD
V
CC
GND
RTSA RTSD
INTA INTD
CSA CSD
TXA TXD
IOW IOR
TXB TXC
CSB
INTB
RTSB
GND
DTRB
CTSB
DSRB
CSC
INTC
RTSC
V
CC
DTRC
CTSC
DSRC
CDB
GND
RIB
D7
RXB
D6
CLKSEL
D5
CDA
RIA
RXA
n.c.
D4
A2
D3
A1
D2
A0
D1
XTAL1
D0
XTAL2
INTSEL
RESET
RXRDY
TXRDY
GND
RXC
RIC
CDC
V
CC
RXD
RID
CDD
002aaa868
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
21
22
23
24
25
26
49
48
47
46
45
44
27
28
29
30
31
32
33
34
35
36
37
6
5
4
3
2
1
68
67
66
65
64
9
8
7
38
39
40
41
42
43
63
62
61
Table 2. Pin description
Symbol Pin Type Description
LQFP64 LQFP80 PLCC68
A0 24 30 34 I Address 0 select bit. Internal registers address selection.
A1 23 29 33 I Address 1 select bit. Internal registers address selection.
A2 22 28 32 I Address 2 select bit. Internal registers address selection.
CDA64 79 9 I Carrier Detect (active LOW). These inputs are associated with
individual UART channels A through D. A logic LOW on these pins
indicates that a carrier has been detected by the modem for that channel.
The state of these inputs is reflected in the Modem Status Register
(MSR).
CDB 18 23 27
CDC 31 39 43
CDD 49 63 61
CLKSEL - 26 30 I Clock Select. CLKSEL selects the divide-by-1 or divide-by-4 prescalable
clock. During the reset, a logic 1 (V
CC
) on CLKSEL selects the
divide-by-1 prescaler. A logic 0 (GND) on CLKSEL selects the divide-by-4
prescaler. The value of CLKSEL is latched into MCR[7] at the trailing
edge of RESET. A logic 1 (V
CC
) on CLKSEL will latch a logic 0 into
MCR[7]. A logic 0 (GND) on CLKSEL will latch a logic 1 into MCR[7].
MCR[7] can be changed after RESET to alter the prescaler value. This
pin is associated with LQFP80 and PLCC68 packages only. This pin is
connected to V
CC
internally on LQFP64 package.
