SC16C754B_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 6 October 2008 18 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
6.6.2 Block DMA transfers (DMA mode 1)
Figure 12 shows TXRDY and RXRDY in DMA mode 1.
6.6.2.1 Transmitter
TXRDY is active when there is a trigger level number of spaces available. It becomes
inactive when the FIFO is full.
6.6.2.2 Receiver
RXRDY becomes active when the trigger level has been reached, or when a time-out
interrupt occurs. It will go inactive when the FIFO is empty or an error in the RX FIFO is
flagged by LSR[7].
6.7 Sleep mode
Sleep mode is an enhanced feature of the SC16C754B UART. It is enabled when EFR[4],
the enhanced functions bit, is set and when IER[4] is set. Sleep mode is entered when:
• The serial data input line, RX, is idle (see Section 6.8 “Break and time-out
conditions”).
• The TX FIFO and TX shift register are empty.
• There are no interrupts pending except THR and time-out interrupts.
Remark: Sleep mode will not be entered if there is data in the RX FIFO.
In Sleep mode, the UART clock and baud rate clock are stopped. Since most registers are
clocked using these clocks, the power consumption is greatly reduced. The UART will
wake up when any change is detected on the RX line, when there is any change in the
state of the modem input pins, or if data is written to the TX FIFO.
Remark: Writing to the divisor latches, DLL and DLM, to set the baud clock, must not be
done during Sleep mode. Therefore, it is advisable to disable Sleep mode using IER[4]
before writing to DLL or DLM.
Fig 12. TXRDY and RXRDY in DMA mode 1
TX
wrptr
wrptr
TXRDY
FIFO full
TXRDY
RX
rdptr
rdptr
FIFO EMPTY
RXRDY
RXRDY
002aaa869
trigger
level
trigger
level
