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SC16C754BIA68,529

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51
SC16C754B_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 6 October 2008 22 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Table 10 lists and describes the SC16C754B internal registers.
[1] These registers are accessible only when LCR[7] = 0.
[2] This bit can only be modified if register bit EFR[4] is enabled, that is, if enhanced functions are enabled.
[3] The Special register set is accessible only when LCR[7] is set to a logic 1.
[4] Enhanced feature register; Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to BFh.
Table 10. SC16C754B internal registers
A2 A1 A0 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read/
Write
General register set
[1]
0 0 0 RHR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R
0 0 0 THR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W
0 0 1 IER 0/
CTS
interrupt
enable
[2]
0/RTS
interrupt
enable
[2]
0/Xoff
[2]
0/X Sleep
mode
[2]
modem
status
interrupt
receive
line status
interrupt
THR
empty
interrupt
RX data
available
interrupt
R/W
0 1 0 FCR RX
trigger
level
(MSB)
RX trigger
level (LSB)
0/TX
trigger
level
(MSB)
[2]
0/TX
trigger
level
(LSB)
[2]
DMA
mode
select
TX FIFO
reset
RX FIFO
reset
FIFO
enable
W
0 1 0 IIR FCR[0] FCR[0] 0/
CTS,
RTS
0/Xoff interrupt
priority
bit 2
interrupt
priority
bit 1
interrupt
priority
bit 0
interrupt
status
R
0 1 1 LCR DLAB break
control bit
set parity paritytype
select
parity
enable
number of
stop bits
word
length
bit 1
word
length
bit 0
R/W
1 0 0 MCR 1× or
1× /4
clock
[2]
TCR and
TLR
enable
[2]
0/Xon Any
[2]
0/enable
loopback
IRQ
enable
OP
FIFO
ready
enable
RTS DTR R/W
1 0 1 LSR 0/error in
RX FIFO
THR and
TSR empty
THR
empty
break
interrupt
framing
error
parity error overrun
error
data in
receiver
R
1 1 0 MSR CD RI DSR CTS ∆CD ∆RI ∆DSR ∆CTS R
1 1 1 SPR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
1 1 0 TCR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
1 1 1 TLR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
1 1 1 FIFO
Rdy
RX FIFO
D status
RX FIFO
C status
RX FIFO
B status
RX FIFO
A status
TXFIFO
D status
TX FIFO
C status
TX FIFO
B status
TX FIFO
A status
R
Special register set
[3]
0 0 0 DLL bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
0 0 1 DLM bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 R/W
Enhanced register set
[4]
0 1 0 EFR auto-CTS auto-RTS special
character
detect
enable
enhanced
functions
[2]
software
flow
control
bit 3
software
flow
control
bit 2
software
flow
control
bit 1
software
flow
control
bit 0
R/W
1 0 0 Xon1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
1 0 1 Xon2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
1 1 0 Xoff1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
1 1 1 Xoff2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
SC16C754B_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 6 October 2008 23 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Remark: Refer to the notes under Table 9 for more register access information.
7.1 Receiver Holding Register (RHR)
The receiver section consists of the Receiver Holding Register (RHR) and the Receiver
Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data
from the RX terminal. The data is converted to parallel data and moved to the RHR. The
receiver section is controlled by the Line Control Register (LCR). If the FIFO is disabled,
location zero of the FIFO is used to store the characters.
Remark: In this case, characters are overwritten if overflow occurs.
If overflow occurs, characters are lost. The RHR also stores the error status bits
associated with each character.
7.2 Transmit Holding Register (THR)
The transmitter section consists of the Transmit Holding Register (THR) and the Transmit
Shift Register (TSR). The THR is actually a 64-byte FIFO. The THR receives data and
shifts it into the TSR, where it is converted to serial data and moved out on the TX
terminal. If the FIFO is disabled, the FIFO is still used to store the byte. Characters are
lost if overflow occurs.
SC16C754B_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 6 October 2008 24 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
7.3 FIFO Control Register (FCR)
This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting
transmitter and receiver trigger levels, and selecting the type of DMA signalling. Table 11
shows FIFO control register bit settings.
Table 11. FIFO control register bits description
Bit Symbol Description
7:6 FCR[7] (MSB),
FCR[6] (LSB)
RX trigger. Sets the trigger level for the RX FIFO.
00 — 8 characters
01 — 16 characters
10 — 56 characters
11 — 60 characters
5:4 FCR[5] (MSB),
FCR[4] (LSB)
TX trigger. Sets the trigger level for the TX FIFO.
00 — 8 spaces
01 — 16 spaces
10 — 32 spaces
11 — 56 spaces
FCR[5:4] can only be modified and enabled when EFR[4] is set. This is
because the transmit trigger level is regarded as an enhanced function.
3 FCR[3] DMA mode select.
logic 0 = set DMA mode 0
logic 1 = set DMA mode 1
2 FCR[2] Reset TX FIFO.
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic (the transmit shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
1 FCR[1] Reset RX FIFO.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
0 FCR[0] FIFO enable.
logic 0 = disable the transmit and receive FIFO (normal default
condition)
logic 1 = enable the transmit and receive FIFO
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51

SC16C754BIA68,529

Mfr. #:
Buy SC16C754BIA68,529
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC 16CB 2.5V-5V 4CH
Lifecycle:
New from this manufacturer.
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