NCN49599MNG Datasheet NCN49599MNG, NCN49599MNTWG, NCN49599PD11GEVK | P19-P21

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Figure 18. Using the ZC_ADJUST register to compensate for zero crossing delay (example for 50 Hz)

The PLL ensures the generated chip clock is in phase with

the rising edge of comparator output. However, these edges

are not precisely in phase with the mains.

Inevitably, the external zero crossing detector circuit

suffers from a delay t

DETD

(e.g. caused by an optocoupler).

In addition, the comparator threshold is not zero (VIR

ZC_IN

= 1.9 V); this results in a further delay, t

COMP0

between the

rising edge of the signal on pin ZC_IN and the rising edge

on the comparator output (as noted before, the PLL takes

only the rising edge into account).

The combination of these delays would cause the modem

to emit and receive data frames too late.

Therefore, the PLL allows tuning the phase difference

between its input and the chip clock. The CHIP_CLK may

be brought forward by setting the register R_ZC_ADJUST.

The adjustment period or granularity is 13 ms, with a

maximum adjustment of 255 • 13 ms = 3,3 ms,

corresponding with a sixth of the 50 Hz mains sine period.

This is illustrated in Figure 9. The “physical frame” (i.e.,

the modulated signal appearing on the mains) starts earlier

with R_ZC_ADJUST[7:0] • 13 ms to compensate for the

zero cross delay.

The delay corresponding with the value of

R_ZC_ADJUST is also listed in Table 21.

Table 21. ZERO CROSSING DELAY COMPENSATION

R_ZC_ADJUST[7:0] Compensation

0000 0000

0 ms (reset value)

0000 0001

13 ms

0000 0010

26 ms

0000 0011

39 ms

... ...

1111 1111

3315 ms

Clock Generator and Timer

The timing generator (Figure 14, centre) is responsible for

all synchronization signals and interrupts related to S−FSK

communication.

The timing is derived from the chip clock (CHIP_CLK,

generated by the PLL) and the main oscillator clock f

CLK

The timing has a fixed repetition rate, corresponding to the

length of a physical subframe (see reference [1]).

When the NCN49599 switches between receive and

transmit mode, the chip clock counter value is maintained.

As a result, the same timing is maintained for reception and

transmission. Seven timing signals are defined:

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• CHIP_CLK is the output of the PLL and the input of

the timing generator. It runs 8 times faster than the bit

rate on the physical interface.

• BIT_CLK is only active at chip clock counter values

that are multiples of 8 (0, 8, .., 2872). It indicates the

start of the transmission of a new bit.

• BYTE_CLK is only active at chip clock counter values

that are multiples of 64 (0, 64, .., 2816). It indicates the

start of the transmission of a new byte.

• FRAME_CLK is only active at counter value 0; it

indicates the transmission or reception of a new frame.

• PRE_BYTE_CLK follows the same pattern as

BYTE_CLK, but precedes it by 8 chip clocks. It can be

used as an interrupt for the internal microcontroller and

indicates that a new byte for transmission must be

generated.

• PRE_FRAME_CLK follows the same pattern at

FRAME_CLK, but precedes it by 8 chip clocks. It can

be used as an interrupt for the internal microcontroller

and indicates that a new frame will start at the next

FRAME_CLK.

• PRE_SLOT is active between the rising edge of

PRE_FRAME_CLK and the rising edge of

FRAME_CLK. This signal can be provided at the

digital output pin DATA/PRES when R_CONF[7] = 0.

Thus, the external host controller may synchronize its

software with the internal FRAME_CLK of the

NCN49599. Refer to the SCI section and Table 26 for

details.

BIT_CLK

63 64 652871 2872 102879 2 3 4 5 6 7 8 9

CHIP_CLK

BYTE_CLK

FRAME_CLK

PRE_FRAME_CLK

PRE_BYTE_CLK

R_CHIP_CNT

PRE_SLOT

Start of the physical subframe

Figure 19. Timing Signals

Transmitter Path Description (S−FSK Modulator)

The NCN49599 transmitter block (Figure 21) generates

the signal to be sent on the transmission channel. Most

commonly, the output is connected to a power amplifier

which injects the output signal on the mains through a

line−coupler.

As the NCN49599 is a half−duplex modem, this block is

not active when the modem is receiving.

The transmitter block is controlled by the microcontroller

core, which provided the bit sequence to be transmitted.

Direct digital synthesis (DDS) is employed to synthesize the

modulated signal (the Sine Wave Generator section); after a

conditioning step, this signal is converted to an analogue

voltage (the DA Converter section). Finally, an amplifier

with variable gain buffers the signal (the Amplifier with

ALC section) and outputs it on pin TX_OUT.

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Transmitter(S−FSK Modulator)

ARM

Interface

Control

TX_OUT

Transmit Data

& Sine Synthesizer

D/A

Filter

ALC

control

ALC_IN

TO RECEIVER

TX_EN

Figure 20. Transmitter Block Diagram

Microcontroller Interface & Control

The interface with the internal ARM microcontroller

consists of an 8−bit data register R_TX_DATA, 2 control

registers R_TX_CTRL and R_ALC_CTRL, a flag

TX_RXB defining the operating mode (a high level

corresponding to transmit mode; low to receive) and the

frequency control registers. All these registers are memory

mapped; most can be accessed through the firmware: refer

to the specific firmware documentation for details.

Sine Wave Generator

The direct digital synthesizer (DDS) generates a

sinusoidal signal alternating between the space frequency

, data 0) and the mark frequency (f

, data 1) as required

to modulate the desired bit pattern. Two 16−bit wide

frequency step registers, R_FM and R_FS, control the steps

used by the DDS and thus the frequencies.

The space and mark frequency can be calculated using

= R_FS[15:0]_dec • f

DDS

= R_FM[15:0]_dec • f

DDS

Equivalently, values for R_FS[15:0] and R_FM[15:0]

may be calculated from the desired carrier frequencies

R_FS[15:0]_dec = [2

• f

DDS

]

R_FM[15:0]_dec = [2

• f

DDS

]

With f

DDS

= 3 MHz the direct digital synthesizer clock

frequency and [x] equal to x rounded to the nearest integer.

At the start of the transmission the DDS phase

accumulator starts at 0, resulting in a 0 V output level.

Switching between f

and f

is phase−continuous. Upon

switching to receive mode the DDS completes the active

sine period. These precautions minimize spurious emissions.

DA Converter and Anti−aliasing Filter

A digital to analogue ΣΔ converter converts the sine wave

digital word to a pulse density modulated (PDM) signal. The

PDM stream is converted to an analogue signal with a first

order switched capacitor filter.

A 3

order continuous time low pass filter in the transmit

path filters the quantization noise and noise generated by the

ΣΔ DA converter.

The −3 dB frequency of this filter can be set to 130 kHz for

applications using the CENELEC A band. In this

configuration, the response of the filter is virtually flat up to

95 kHz. Alternatively a −3 dB frequency of 195 kHz can be

selected yielding a flat response for the entire CENELEC A

to D band (i.e., up to 148.5 kHz). Refer to the documentation

of the firmware for more information.

The low pass filter is tuned automatically to compensate

for process variation.

Amplifier with Automatic Level Control (ALC)

The analogue output of the low−pass filter is buffered by

a variable gain amplifier; 8 attenuation steps from 0 to

−21 dB (typical) with steps of 3 dB are provided.

The attenuation can be fixed by setting the bit

R_ALC_CTRL[3]. The embedded microcontroller can then

set the attenuation using register ALC_CTRL[2:0]. This

application microcontroller. The attenuations corresponding

to R_ALC_CTRL[2:0] values are given in Table 34.

Table 22. FIXED TRANSMITTER OUTPUT ATTENUATION

ALC_CTRL[2:0] Attenuation

000 0 dB

001 −3 dB

010 −6 dB

011 −9 dB

100 −12 dB

101 −15 dB

110 −18 dB

111 −21 dB

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P35

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Network Controller & Processor ICs 3 DIE MCM CONTAINING PLDA

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