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NCN49599MNG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35
NCN49599
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4
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating Symbol Min Max Unit
POWER SUPPLY PINS VCC, VDD, VDD2, VDDA, VSS, VSSA
Absolute maximum power amplifier supply
V
CC_ABSM
V
EE
− 0.3 13.2 V
Absolute maximum digital amplifier power supply V
DD_ABSM
V
SS
− 0.3 3.9 V
Absolute maximum digital modem power supply V
DD_ABSM
V
SS
− 0.3 3.9 V
Absolute maximum analog power supply V
DDA_ABSM
V
SSA
− 0.3 3.9 V
Absolute maximum difference between digital and analog power supply V
DD
− V
DDA_ABSM
−0.1 0.1 V
Absolute maximum difference between digital and analog ground V
SS
− V
SSA_ABSM
−0.1 0.1 V
Absolute maximum difference between digital and power ground V
SS
− V
EE_ABSM
−0.5 0.5 V
CLOCK PINS XIN, XOUT
Absolute maximum input for the clock input pin (Note 1)
V
XIN_ABSM18
V
SS
− 0.2 V
DD18
+ 0.2 V
Absolute maximum voltage at the clock output pin (Note 1) V
XOUT_ABSM18
V
SS
− 0.2 V
DD18
+ 0.2 V
NON 5 V SAFE PINS: TX_OUT, ALC_IN, RX_IN, RX_OUT, REF_OUT, ZC_IN, TDO, SCK, SDO, SCB
Absolute maximum input for normal digital inputs and analog inputs
V
N5VSIN_ABSM
V
SS
− 0.3 V
DD
+ 0.3 V
Absolute maximum voltage at any output pin V
N5VSOUT_ABSM
V
SS
− 0.3 V
DD
+ 0.3 V
Maximum peak input current at the zerocrossing input pin Imp
ZC_IN
−20 20 mA
Maximum average input current at the zerocrossing input pin (1 ms) Imavg
ZC_IN
−2 2 mA
5 V SAFE PINS: TX_ENB, TXD, RXD, BR0, BR1, IO0..IO9, RESB, TDI, TCK, TMS, TRSTB, TEST, SDI
Absolute maximum input for digital 5 V safe pins configured as input (Note 2)
V
5VSIN_ABSM
V
SS
− 0.3 5.5 V
Absolute maximum voltage at 5V safe pin configured as output (Note 2) V
5VSOUT_ABSM
V
SS
− 0.3 V
DD
+ 0.3 V
AMPLIFIER PINS A+, A−, B+, B−, BOUT1, BOUT2, VWARN, XOUT
Absolute maximum voltage at the analog amplifier pins
V
AMPA_ABSM
V
SS
− 0.3 V
DD18
+ 0.3 V
Absolute maximum voltage at the amplifier control pins V
AMPC_ABSM
V
SS
− 0.3 V
CC
+ 0.3 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The upper maximum voltage rating on the clock pins XIN and XOUT is specified with respect to the output voltage of the internal core voltage
regulator. The tolerance of this voltage regulator must be taken into account. In case an external clock is used, care must be taken not to
damage the XIN pin.
2. The direction (input or output) of configurable pins (IO0...IO9) depends on the firmware.
Normal Operating Conditions
Operating ranges define the limits for functional
operation and parametric characteristics of the device as
described in the Electrical Characteristics section and for the
reliability specifications.
Total cumulative dwell time outside the normal power
supply voltage range or the ambient temperature under bias,
must be less than 0.1 percent of the useful life.
Table 3. OPERATING RANGES
Rating Symbol Min Max Unit
Power supply voltage range (VDDA and VDD pins) V
DD
, V
DDA
3.0 3.6 V
Power supply voltage range (VCC pin) Vcc 6.0 12.0 V
Junction Temperature Range T
J
−40 125 °C
Ambient Temperature Range T
A
−40 85 °C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
NCN49599
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Pin Description − QFN Package
TXD/PRES
NCN49599
1
2
3
4
5
6
7
8
9
10
11
12
13
27
26
25
24
23
22
21
20
19
18
17
16
15
42
41
40
39
38
37
36
35
34
33
32
31
30
44
45
46
47
48
49
50
51
52
53
54
55
56
14
28
29
43
VEE
B_OUT2
B_OUT1
VCC
A_OUT
A−
A+
ZC_IN
REF_OUT
RX_IN
RX_OUT
VSSA
TDI
IO6
IO7
EXT_CLK_EN
XIN
XOUT
VDD1V8
VSS
VDD
TXD
RXD
TMS
TDO
IO5
IO4
IO3
VSS
VDD
ILIM
RLIM
VEE
B+
B−
SDO
CSB
IO2
SEN
BR1
BR0
IO1
TEST
TX_OUT
ALC_IN
RES
TRST
IO0
TCK
SCK
SDI
NC
VDDA
TX_EN
EN
Figure 2. QFN Pin−out of NCN49599 (top view)
Table 4. NCN49599 QFN PIN FUNCTION DESCRIPTION
Pin Number Pin Name I/O Type Description
1 B− In A Inverting input of operational amplifier B
2 B+ In A Non−inverting input of operational amplifier B
3, 56 VEE P Negative power supply amplifiers
4 RLIM In A Amplifier B current limit set resistor pin
5 ILIM In A Current limit flag
6, 25 VDD P 3.3 V digital supply
7, 24 VSS In P Digital ground
8..10, 17, 18 IO3...IO7 In/Out D, 5VS, ST General−purpose I/O’s (Note 3)
11, 36 IO0, IO1 In/Out D, 5VS, ST General−purpose I/O’s (Notes 3 and 4)
12 TDO Out D JTAG test data output
13 TDI In D, 5VS, PD, ST JTAG test data input (Note 7)
14 TCK In D, 5VS, PD JTAG test clock (Note 7)
15 TMS In D, 5VS, PD JTAG test mode select (Note 7)
16 TRSTB In D, 5VS, PD, ST JTAG test reset (active low) (Note 8)
19 EXT_CLK_EN In D, 5VS, PD, ST External clock enable input
20 TXD/PRES Out D, 5VS Output of transmitted data (TXD) or PRE_SLOT signal (PRES)
21 XIN In A, 1.8V Crystal oscillator input
22 XOUT Out A, 1.8V Crystal oscillator output (output must be left floating when XIN is
driven by external clock)
3. The direction and function of the general−purpose I/O’s is controlled by the firmware. Depending on the firmware behavior, a general− purpose
IO (GPIO) used as an output may appear as an open−drain, push−pull or open−source pin. Refer to the firmware documentation for details.
4. During boot (i.e., before firmware has been uploaded) this pin is an output and indicates the status of the boot loader. Once firmware has
been loaded, the pin is available as a GPIO.
5. During normal operation, this pin must be tied to ground (recommended) or left open.
6. If the modem is not loading the firmware from an external SPI memory, it is recommended that this pin is tied to ground or Vdd.
7. During normal operation, it is recommended that this pin is tied to ground.
8. During normal operation, this pin must be tied to Vdd.
9. If a general purpose IO is configured as an output, the pull−down resistor is disconnected.
NCN49599
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Table 4. NCN49599 QFN PIN FUNCTION DESCRIPTION
Pin Number DescriptionTypeI/OPin Name
23 VDD1V8 P
1.8 V regulator output. A decoupling capacitor of at least 1 mF is
required for stability
26 TXD Out D, 5VS, OD UART transmit output
27 RXD In D, 5VS UART receive input
28 SCK Out D, 5VS SPI interface to external Flash: clock
29 SDI In D, 5VS, ST SPI interface to external Flash: serial data input (Note 6)
30 SDO Out D, 5VS SPI interface to external Flash: serial data output
31 CSB In D, 5VS SPI interface to external Flash: chip select
32 IO2 In/Out D, 5VS, ST Must be kept low while firmware is loaded over the serial inter-
face; available as a normal GPIO afterwards (Note 3)
33 SEN In D, 5VS, PD, ST Boot mode selection (refer to Boot Loader section)
34 BR1 In D, 5VS UART baud rate selection
35 BR0 In D, 5VS UART baud rate selection
37 RESB In D, 5VS, ST Reset (active low)
38 TEST In D, 5VS, ST, PD Production hardware test enable (Note 5)
39 TX_ENB Out D, 5VS, OD Transmit enable (active low)
40 NC This pin is not connected and must be connected to ground (recommended) or left open
41 TX_OUT Out A Transmitter output
42 ALC_IN In A Automatic level control input
43 VDDA P 3.3 V analog supply
44 VSSA P Analog ground
45 RX_OUT Out A Output of receiver operational amplifier
46 RX_IN In A Non−inverting input of receiver operational amplifier
47 REF_OUT Out A
Internal voltage reference. A decoupling capacitor of at least 1 mF
is required for stability
48 ZC_IN In A 50/60 Hz input for mains zero crossing detection
49 ENB In D Enable / shutdown power amplifier (active low)
50 A+ In A Non−inverting input of operational amplifier A
51 A− In A Inverting input of operational amplifier A
52 A_OUT Out A Output of operational amplifier A
53 VCC P Positive supply for power amplifiers A and B
54 B_OUT1 Out A Output of operational amplifier B
55 B_OUT2 Out A Output of operational amplifier B
3. The direction and function of the general−purpose I/O’s is controlled by the firmware. Depending on the firmware behavior, a general− purpose
IO (GPIO) used as an output may appear as an open−drain, push−pull or open−source pin. Refer to the firmware documentation for details.
4. During boot (i.e., before firmware has been uploaded) this pin is an output and indicates the status of the boot loader. Once firmware has
been loaded, the pin is available as a GPIO.
5. During normal operation, this pin must be tied to ground (recommended) or left open.
6. If the modem is not loading the firmware from an external SPI memory, it is recommended that this pin is tied to ground or Vdd.
7. During normal operation, it is recommended that this pin is tied to ground.
8. During normal operation, this pin must be tied to Vdd.
9. If a general purpose IO is configured as an output, the pull−down resistor is disconnected.
P: Power pin 5VS: 5 V safe; pin that supports the presence of 5 V if used as input or as open−drain output
A: Analogue pin Out: Output signal
D: Digital pin In: Input signal
PD: Internal Pull Down resistor (Note 9)
OD: Open Drain Output
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35

NCN49599MNG

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Manufacturer:
ON Semiconductor
Description:
Network Controller & Processor ICs 3 DIE MCM CONTAINING PLDA
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