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NCN49599MNG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35
NCN49599
www.onsemi.com
7
ELECTRICAL CHARACTERISTICS
All parameters are valid for T
J
= −40°C to 125°C, V
DD
= 3.3 V, V
CC
= 12 V, V
EE
= 0 V, f
CLK
= 48 MHz ± 50 ppm unless otherwise specified.
Internal voltage regulator: pin VDD1V8
Table 5. POWER SUPPLY AND VOLTAGE REFERENCE
Parameter Test Conditions Symbol Min Typ Max Unit
Internal voltage regulator output V
DD18
1.62 1.80 1.98 V
V
DD
and V
DDA
current consumption
During reception (Note 10) I
RX
40 60 mA
During transmission (Note 10) I
TX
40 60 mA
RESB = 0 I
RESET
4 mA
V
CC
quiescent current consumption
ENB = 0; no load I
Q_EN
20 40 mA
ENB = 1 I
Q_HiZ
120 150
mA
10.With typical firmware. The exact value depends on the firmware variant loaded and the firmware configuration.
Oscillator: pin XIN, XOUT
In production the actual oscillation of the oscillator and duty cycle will not be tested. The production test will be based on
the static parameters and the inversion from XIN to XOUT in order to guarantee the functionality of the oscillator.
Table 6. OSCILLATOR
Parameter Test Conditions Symbol Min Typ Max Unit
Duty cycle with quartz connected 35 65 %
Start−up time T
startup
15 ms
Load capacitance external crystal C
L
18 pF
Series resistance external crystal R
S
1 6 60
W
Maximum Capacitive load on XOUT XIN used as clock input CL
XOUT
15 pF
Low input threshold voltage XIN used as clock input VIL
XOUT
0.3 V
DD18
V
High input threshold voltage XIN used as clock input VIH
XOUT
0.7 V
DD18
V
Low output voltage XIN used as clock input,
XOUT = 2 mA
VOL
XOUT
0.3 V
High input voltage XIN used as clock input VOH
XOUT
V
DD18
−
0.3
V
Rise and fall time on XIN XIN used as clock input t
rXIN_EXT
1.5 ns
Zero Crossing detector and 50/60 Hz PLL: pin ZC_IN
Table 7. ZERO CROSSING DETECTOR AND 50/60 HZ PLL
Parameter Test Conditions Symbol Min Typ Max Unit
Mains voltage input range With protection resistor at
ZC_IN (Note 11)
V
MAINS
90 550 V
PK
Rising threshold level VIR
ZC_IN
1.9 V
Falling threshold level VIF
ZC_IN
0.85 V
Hysteresis VHY
ZC_IN
0.4 V
Lock range (Note 12) R_CONF[0] = 0 (50 Hz) Flock
50Hz
45 55 Hz
R_CONF[0] = 1 (60 Hz) Flock
60Hz
54 66 Hz
Lock time (Note 12) R_CONF[0] = 0 (50 Hz) Tlock
50Hz
15 s
R_CONF[0] = 1 (60 Hz) Tlock
60Hz
20 s
11. This parameter is not tested in production.
12.These parameters will not be measured in production as the performance is determined by a digital circuit. Correct operation of this circuit
will be guaranteed by the digital test patterns.
NCN49599
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8
Table 7. ZERO CROSSING DETECTOR AND 50/60 HZ PLL
Parameter UnitMaxTypMinSymbolTest Conditions
Frequency variation without going out of
lock (Note 12)
R_CONF[0] = 0 (50 Hz) DF
60Hz
0.1 Hz/s
Frequency variation without going out of
lock (Note 12)
R_CONF[0] = 1 (60 Hz) DF
50Hz
0.1 Hz/s
Jitter of CHIP_CLK (Note 12) Jitter
CHIP_CLK
25
ms
11. This parameter is not tested in production.
12.These parameters will not be measured in production as the performance is determined by a digital circuit. Correct operation of this circuit
will be guaranteed by the digital test patterns.
Transmitter External Parameters: pin TX_OUT, ALC_IN, TX_ENB
Table 8. TRANSMITTER EXTERNAL PARAMETERS
Parameter Test Conditions Symbol Min Typ Max Unit
AC output level f
TX_OUT
= 23 – 75 kHz (Note 13)
f
TX_OUT
= 148.5 kHz (Note 13)
V
TX_OUT
0.85
0.76
1.15
1.22
V
PK
V
PK
DC output level V
TX_OUT
1.65 V
Second order harmonic distortion f
TX_OUT
= 148.5 kHz (Note 13) HD2 −55 dB
Third order harmonic distortion f
TX_OUT
= 148.5 kHz (Note 13) HD3 −57 dB
Transmitted carrier frequency resolution Rf
TX_OUT
11.44 11.44 Hz
Transmitted carrier frequency accuracy (Note 14) Df
TX_OUT
30 Hz
Capacitive output load at pin TX_OUT (Note 14) CL
TX_OUT
20 pF
Resistive output load at pin TX_OUT RL
TX_OUT
5 5
kW
Turn off delay of TX_ENB output Td
TX_ENB
0.25 0.5 ms
Automatic level control attenuation step ALC
step
2.9 3.1 dB
Maximum attenuation ALC
range
20.3 21.7 dB
Low threshold level on ALC_IN With DC bias equal to V
REF_OUT
VTL
ALC_IN
0.34 0.46 V
PK
High threshold level on ALC_IN With DC bias equal to V
REF_OUT
VTH
ALC_IN
0.54 0.72 V
PK
Input impedance of ALC_IN pin R
ALC_IN
111 189
kW
Power supply rejection ratio of the
transmitter section
f = 50 Hz (Note 15)
f = 10 kHz (Note 15)
PSRR
TX_OUT
32
10
dB
Transmit cascade gain
(Note 16)
f = 10 kHz
f = 148.5 kHz
f = 195 kHz
f = 245 kHz
f = 500 kHz
f = 1 MHz
f = 2 MHz
V
TX_PF_10kHz
V
TX_LPF_148kHz5
V
TX_LPF_195kHz
V
TX_LPF_245kHz
V
TX_LPF_500kHz
V
TX_LPF_1000kHz
V
TX_LPF_2000kHz
−0.5
−1.3
−4.5
−36
−50
0.5
0.5
−1.5
−3
−18
dB
13.With the level control register set for maximal output amplitude. Tested with low pass filter tuned for CENELEC D−band.
14.This parameter will not be tested in production.
15.A sinusoidal signal of 100 mVpp is injected between VDDA and VSSA while the digital AD converter generates an idle pattern. The signal
level at TX_OUT is measured to determine the parameter.
16.The cascade of the digital−to−analog converter (DAC), low−pass filter (LPF), and transmission amplifier is production tested and must have
a frequency characteristic between the limits listed. The level is specified relative to the level at DC; the absolute output level will depend
on the operating condition.
This test is done with the low−pass filter (LPF) tuned to include the CENELEC D−band. In production the measurement will be done for relative
to DC with a signal amplitude of 100 mV.
NCN49599
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9
Power amplifier parameters: Pin A+, A−, A_OUT, B+, B−, BOUT1&2, VSS, VEE, ENB, ILIM, RLIM
Table 9. POWER AMPLIFIER GENERAL PARAMETERS
Parameter Test Conditions Symbol Min Typ Max Unit
Output shutdown time ENB 0 → 1 60 ns
Output enable time ENB 1 → 0 5 10
ms
Junction temperature shutdown threshold (Note 17) +150 +160 °C
Junction temperature shutdown recovery
threshold
(Note 17) +135 °C
ENB input level high V
IH,EN
2 V
ENB input level low V
IL,EN
0.8 V
ENB input current
V
ENB
= 3.3 V 10
mA
V
ENB
= 0 V 0.1
mA
ILIM flag output high level V
IH,EN
2 V
ILIM flag output low level V
IL,EN
0.8 V
17.Characterization data only. Not tested in production.
Table 10. POWER AMPLIFIER EXTERNAL PARAMETERS OP AMP A
Parameter Test Conditions Symbol Min Typ Max Unit
Input offset voltage V
OS,A
±3 ±10 mV
Offset vs power supply V
CC
= +6 V, V
EE
= −6 V PSRR
A
25 150
mV/V
Input bias current (Note 18) I
B,A
1 nA
Input voltage noise density f = 1 kHz, V
IN
= GND,
BW = 131 kHz (Note 18)
e
n,A
250 nV/√Hz
Common−mode voltage range V
CM,A
V
EE
−0.1 V
CC
− 3 V
Common−mode rejection ratio V
EE
− 0.1 v V
CM
v V
CC
− 3 CMRR
A
70 85 dB
Differential input impedance Z
IDM,A
0.2 | 1.5
GW | pF
Common−mode input impedance Z
ICM,A
0.2 | 3
GW | pF
Open−loop gain
R
L
= 500 W (Note 18)
A
OL,A
80 100 dB
Gain bandwidth product GBW
A
80 MHz
Full power bandwidth G = +5, V
out
= 11 V
PP
(Note 18) 0.2 1.5 MHz
Slew rate SR
A
60
V/ ms
Total harmonic distortion and noise
G = +1, R
L
= 500 W, V
O
= 8 V
PP
, f =
1 kHz, C
IN
= 220 mF, C
OUT
= 330 mF
THD+N
A
0.015 %
G = +1, R
L
= 50 W, V
O
= 8 V
PP
, f =
100 kHz, C
IN
= 220 mF, C
OUT
= 330 mF
THD+N
A
0.023 %
Voltage output swing from rail V
CC
= +12 V, V
EE
= 0 V
From positive rail
IL = -12 mA
V
OH,A
0.3 1 V
From negative rail IL = +12 mA V
OL,A
0.3 1 V
Short−circuit current I
SC,A
280 mA
Output impedance Closed Loop G = +4, f = 100 kHz Z
O,A
0.25
W
Capacitive load drive C
LOAD,A
100 pF
18.Characterization data only. Not tested in production.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35

NCN49599MNG

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Manufacturer:
ON Semiconductor
Description:
Network Controller & Processor ICs 3 DIE MCM CONTAINING PLDA
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