NCN49599
www.onsemi.com
28
Communication Controller
ARM
Risc
Core
POR
Watchdog
Timer 1 & 2
Interrupt
Control
Program
ROM
RESB
PC20120530.4
FROM
RECEIVER
TO
TRANSMIT
Flash SPI
Serial
Comm.
Interface
TxD
RxD
BR0
BR1
Local Port
IO[9:0]
DATA /PRES
TEST
Test
Control
CSB
SDO
SDI
Data / Program
RAM
SEN
SCK
Figure 32. The communication controller is based on a standard ARM Cortex M0 core
The processor is an ARM Cortex M0 32−bit core with a
reduced instruction set computer (RISC) architecture,
optimized for IO handling. Most instructions complete in a
single clock cycle, including byte multiplication. The
peripherals include a watchdog, test and debug control,
RAM, ROM containing the boot loader, UART, two timers,
an SPI interface to optional external memory, I/O ports and
the power−on reset. The microcontroller implements
interrupts.
The 32 kB RAM contains the necessary space to store the
firmware and the working data. A full−duplex serial
communication block (the SCI section) allows interfacing to
the application microcontroller.
Local Port
Ten bidirectional general purpose input/output (GPIO)
pins (IO0..IO9) are provided. All general purpose IO pins
can be configured as an input or an output. In addition, the
firmware can emulate open−drain or open−source pins. All
pins are 5 V tolerant.
When the modem is booting, IO2 is configured as an input
and must be pulled low to enable uploading firmware over
the serial interface. At the same time, IO0 and IO1 are
configured as outputs and show the status of the boot loader.
A LED may be connected to IO0 to help with debugging.
After the firmware has been loaded successfully, IO0..IO2
become available as normal IOs.
Typically, the firmware provides status indication on
some IO pins; other IO pins remain available to the
application microcontroller as IO extensions.
The application microcontroller has also low−level access
to internal timing of the modem through the digital output
DATA/PRES pin. The function of this pin depends on the
register bit R_CONF[7].
If the bit is cleared (0), the preslot synchronization signal
(PRE_SLOT) appears on the pin.
If the bit is set (1), the modem outputs the baseband,
unmodulated, data. Thus, DATA/PRES is driven high when
a space symbol is being transmitted (i.e., the space
frequency f
S
appears on pin TX_OUT); it is driven low when
a mask symbol is transmitted (f
M
on TX_OUT).
Testing
A JTAG debug interface is provided for development,
debugging and production test. An internal pull−down
resistor is provided on the input pins (TDI, TCK, TMS, and
TRSTB).
In practice, the end user of the modem will not need this
interface; this input pins may be tied to ground
(recommended) or left floating; TDO should be left floating.
The pin TEST enables the internal hardware test mode
when driven high. During normal operation, it should be tied
to ground (recommended) or left floating.
Serial Communication Interface (SCI)
The Serial Communication Interface allows
asynchronous communication with any device
incorporating a standard Universal Asynchronous Receiver
Transmitter (UART).
The serial interface is full−duplex and uses the standard
NRZ format with a single start bit, eight data bits and one
stop bit (Figure 34). The baud rate is programmable from
9600 to 115200 baud through the BR0 and BR1 pins.
