NCN49599
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31
Bootloader
SDO
NCN49599
SDI
SCK
SDI
SD0
SCK
EEPROM
LE25U20AQGTXG
CSB
CSB
Figure 37. Connecting an External SPI Memory to the Modem
The memory must be connected to the pins of the
dedicated serial peripheral interface (SPI), as shown in
Figure 37. Connecting an external SPI memory to the
modem. Figure 37. Any non−volatile memory with the
standard command set and three bytes addressing is
supported; is recommended.
The user must program the firmware into the external
memory starting from address 0. Four bytes must be added
at the end of the lowest 256−byte sector that can fit them, i.e.
either the sector containing the last byte of the firmware or
the next sector. These four bytes contain the checksum, the
number of sectors used, and the magical numbers A5
H
and
5A
H
. The checksum must be computed over the entire binary.
Between the four metadata bytes and the firmware,
zero−padding must be written.
This is illustrated in Table 26.
Table 26. Required contents of an external bootable SPI
memory for a binary firmware file of length N bytes
Address Content
0
Firmware binary
...
N
N + 1
Zero padding, if required
...
100
H
S + FB
H
100
H
S + FC
H
Checksum
100
H
S + FD
H
S, the number of sectors used
100
H
S + FE
H
Magical number: A5
H
100
H
S + FF
H
Magical number: 5A
H
Where S is the number of sectors used:
The tool PlcEepromGenerator.exe, provided by
ON Semiconductor, may be used to convert a binary
firmware file into a file that follows these requirements. The
latter can be written directly in the external memory.
As an example, if the firmware binary size is 618 bytes,
the first two 256−byte sector will be filled completely. The
last 106 bytes of the firmware binary will be written to the
third sector, followed by zero padding (256 − 106 − 4 = 146
bytes), followed by four bytes: checksum, 03
H
, A5
H
and
5A
H
.
Once the boot loader has finished copying the firmware to
the internal memory, the checksum is calculated and
compared to the stored checksum. If both match, the
processor is released from reset and the firmware starts
executing. IO2 subsequently becomes available as a normal
GPIO.
Firmware Upload Over the Serial Communication
Interface
During reset, the boot loader module in the modem can
receive the firmware over the serial interface.
To enable this mode, the IO2 and the boot control pin SEN
must be driven low; subsequently the modem must be reset.
IO2 must remain low during the entire boot process; if
driven high during boot the boot loader terminates
immediately. To restart the boot loader, reset the modem.
As soon as the reset of the modem is released, the boot
loader process starts. When it is ready to receive the
firmware from the external microcontroller, the boot loader
will send a 02
H
(STX) byte.
Upon receiving this byte the user must send the byte
sequence specified in Table 27. The sequence contains a
checksum to verify correctness of the received binary image.
The CRC must be calculated over the firmware binary only
(excluding the magical number and the size). The program
crc.exe, provided by ON Semiconductor, can be used for this
calculation.
NCN49599
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32
Table 27. Byte sequence to be transmitted by the
application microcontroller during firmware upload
Value Description
[ CE
H
] Should only be sent to restart the boot
loader process, in response to a NAK
character received from the modem
AA
H
Magical number
Size (LSB)
The size of the entire firmware binary,
including the four bytes for the CRC at
the end
Size (MSB)
Binary, first byte
Contents of the firmware binary
...
Binary, last byte
CRC (LSB)
CRC, as calculated on the binary only
CRC (MSB)
Data transmission must start only after receiving the STX
byte. In addition, the first byte must be sent within 350 ms.
If these timing constraints are not satisfied the boot loader
will send a 15
H
(NAK) character and will reject any data
received until the application microprocessor stops sending
bytes for at least 100ms. The pause will restart the boot
loader, and a new STX character will be sent to the
application microcontroller to indicate this.
Once transmission has started, the maximal delay
between consecutive bytes is 20 ms. If this timing
constraints is not met, or if the checksum is incorrect, the
boot loader will send a 15
H
(NAK) character. This error also
occurs when the user attempts to upload a binary exceeding
the maximal size of 7F00
H
(32512) bytes. When the
application microcontroller receives this NAK, it should
transmit a CE
H
(mnemonic for ”clear error”) byte. This
informs the boot loader that the application microcontroller
understood the problem. Following the CE
H
byte, the
microcontroller may restart.
The timing constraints are illustrated in Figure 3.
APPLICATION INFORMATION
For a system−level overview of power line
communication, refer to [7]. For more information on how
to design with the NCN49599 modem, refer to the design
manual available from your sales representative [1]. This
section gives a few hints.
Supplies and Decoupling
For optimal stability and noise rejection, all power
supplies must be decoupled as physically close to the device
as possible.
The line driver is primarily powered through the pin VCC.
Large currents are drawn from this supply rail if the
amplifiers are loaded. Two ceramic capacitors of 10 mF and
100 nF to ground are recommended at this point (Figure 38).
Of course, the 100 nF capacitor must be nearest to the
device.
Figure 38. Decoupling Capacitors − Line Driver
NCN49599
100 nF
B+
B−
54
55
2
1
VCC
6
3.3 V
53
VCC
56
3
VEE
12 V
FB
10 mF
The analogue and digital blocks of the modem itself are
powered through independent power supply pins (VDDA
resp. VDD); the nominal supply voltage is 3.3 V. On both
pins, decoupling must be provided with at least a ceramic
capacitor of 100 nF between the pin and the corresponding
ground (VSSA resp. VSS). The connection path of these
capacitors on the printed circuit board (PCB) should be kept
as short as possible in order to minimize the parasitic
inductance.
It is recommended to tie both analogue and digital ground
pins to a single, uninterrupted ground plane.
NCN49599
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33
1
2
3
4
5
6
7
8
9
10
11
12
13
27
26
25
24
23
22
21
20
19
18
17
16
15
42
41
40
39
38
37
36
35
34
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32
31
30
44
45
46
47
48
49
50
51
52
53
54
55
56
14
28
29
43
VEE VCC REF_OUT
VDD
VDD
VEE
PC20120831.1
VSSA VDDA
VDD1V8
VSS
C
18
C
20
C
11
ANALOG
GROUND
3,3V SUPPLY
3,3V SUPPLY
C
15
NC
12V SUPPLY
POWER
GROUND
VSS
C
19
3,3V SUPPLY
C
21
Figure 39. Recommended layout of the placement of decoupling capacitors (bottom ground plane not shown)
Internal Voltage Reference
REF_OUT is the analogue output pin which provides the
voltage reference used by the A/D converter. This pin must
be decoupled to the analogue ground by a 1 mF ceramic
capacitance C
DREF
. The connection path of this capacitor to
the V
SSA
on the PCB should be kept as short as possible in
order to minimize the serial inductance.
Internal Voltage Regulator
An internal linear regulator provides the 1.8 V core
voltage for the microcontroller. This voltage is connected to
pin VDD1V8. A ceramic decoupling capacitor of 1 mF to
ground must be connected as close as possible to this pin
(Figure 39).
The internal regulator should not be used to power other
components.
Exposed Thermal Pad
The line driver output amplifier in the NCN49599 is
capable of delivering 1.5 A into a complex load.
Output signal swing should be kept as high as possible.
This will minimize internal heat generation, reducing the
internal junction temperature. The line driver in the
NCN49599 can swing to within 1 V of either rail without
adding distortion.
An exposed thermal pad is provided on the bottom of the
device to facilitate heat dissipation. The printed circuit
board and soldering process must be carefully designed to
minimize the thermal resistance between the exposed pad
and the ambient. Refer to [1,8] for more information.
Table 28. DEVICE ORDERING INFORMATION
Part Number Temperature Range Package Type Shipping
NCN49599MNG −40°C – 125°C QFN−56 Tube
NCN49599MNRG −40°C – 125°C QFN−56 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

NCN49599MNG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Network Controller & Processor ICs 3 DIE MCM CONTAINING PLDA
Lifecycle:
New from this manufacturer.
Delivery:
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