© Semiconductor Components Industries, LLC, 2010
January, 2017 Rev. 5
1 Publication Order Number:
MT9D115/D
MT9D115
MT9D115 1/5‐inch
System‐On‐a‐Chip (SOC)
CMOS Digital Image Sensor
Table 1. KEY PERFORMANCE PARAMETERS
Parameter Typical Value
Pixel Size
1.75 mm × 1.75 mm
Optical Format 1/5-inch
Array Format (Active) 1600 (H) × 1200 (V) = 1.92 Mp
Imaging Area 2.8 mm × 2.10 mm,
3.50 mm Diagonal (4:3 Aspect Ratio)
CRA 25°
Color Filter Array RGB Bayer
Scan Mode Progressive
Shutter Electronic Rolling Shutter (ERS)
Input Clock Range 6–54 MHz
Output Pixel Clock Maximum 85 MHz
Output MIPI Data Rate Maximum 512 Mb/s
Max. Frame Rate 15 fps Full Res
30 fps 800 x 600
Responsivity 0.65 V/Luxsec (550 nm)
Signal-to-Noise Ratio 39 dB (MAX)
Dynamic Range 63.9 dB (Pixel)
Supply Voltage
Digital
Analog
I/O
MIPI
1.8 V (Nominal)
2.8 V (Nominal)
1.8 V or 2.8 V (Nominal)
1.71.95 V
Power Consumption 196 mW (Note 1)
Operating Temperature Range –30°C to 70°C (at Junction)
Package Bare Die, CSP
1. Power consumption for typical voltages at 800 × 600 video mode.
Features
2 Mp Resolution (1600 (H) × 1200 (V))
1/5-inch Optical Format
Same or Better Image Quality Compared to MT9D112
Individual Module ID Support Through One-time Programmable
(OTP) Memory
Surface Fit Lens Correction (LC) to Compensate for Lens/Small
Pixel Vignetting and Corner Color Variations
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Automatic Functions: Exposure, White
Balance, Black Level Offset Correction,
Flicker Detection and Avoidance, Color
Saturation Control, Defect Identification an
d
Correction, Aperture Correction, and GPIO
Programmable Controls: Exposure, White
Balance, Horizontal and Vertical Blanking,
Color, Sharpness, Gamma, Lens Shading
Correction, Horizontal and Vertical Image
Flip, Zoom, Windowing, Sampling Rates,
and GPIO
15 Frames per Second (fps) at
1600(H) × 1200 (V) with Moderate Pixel
Clock Frequency ( 64 MHz) to Minimize
Baseband Reception Interference and 30 fp
s
at 800 (H) × 600 (V)
2 × 2 Pixel Binning to Improve Low-light
Image Quality
Support for External LED or Xenon Flash
On-chip Phase-locked Loop (PLL) to
Minimize the Number of System Clocks
Low Power Modes to Prolong Battery Life
of Portable Devices
Fail-safe I/Os with Programmable Output
Slew Rate
Industry Standard Two-wire Serial Interface
for Controls
10-bit Parallel or MIPI Serial Interfaces for
Image Data
Applications
Cellular Phones
PC Cameras
PDAs
See detailed ordering and shipping information on page 2 of
this data sheet.
ORDERING INFORMATION
MT9D115
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2
ORDERING INFORMATION
Table 2. AVAILABLE PART NUMBERS
Part Number Product Description Orderable Product Attribute Description
MT9D115D00STCK25AC1200 2 MP 1/5 SOC
Die Sales, 200 mm Thickness
MT9D115EB3STCCR 2 MP 1/5 CIS SOC Chip Tray without Protective Film
MT9D115W00STCK25AC1750 2 MP 1/5 SOC
Wafer Sales, 750 mm Thickness
FUNCTIONAL DESCRIPTION
The ON Semiconductor MT9D115 is a 1/5-inch 2 Mp
CMOS digital image sensor with an integrated advanced
camera system. This camera system features
a microcontroller (MCU), a sophisticated image flow
processor (IFP), MIPI and parallel output ports (only one
output port can be used at a time). The microcontroller
manages all functions of the camera system and sets key
operation parameters for the sensor core to optimize the
quality of raw image data entering the IFP. The IFP will be
responsible for processing and enhancing the image.
The entire system-on-a-chip (SOC) has superior low-light
performance that is particularly suitable for PC camera
applications. The MT9D115 features ON Semiconductors
breakthrough low-noise CMOS imaging technology that
achieves near-CCD image quality (based on signal-to-noise
ratio and low-light sensitivity) while maintaining the
inherent size, cost, and integration advantages of CMOS.
The ON Semiconductor MT9D115 can be operated in its
default mode or programmed for frame size, exposure, gain,
and other parameters. The default mode output is
a 800 × 600 image size at 30 frames per second (fps),
assuming a 24 MHz input clock. It outputs 8-bit data, using
the parallel output port.
ARCHITECTURE OVERVIEW
The MT9D115 combines a 2 Mp sensor core with an IFP
to form a stand-alone solution for both image acquisition
and processing. Both the sensor core and the IFP have
internal registers that can be controlled by the user. In
normal operation, an integrated microcontroller
autonomously controls most aspects of operation.
The processed image data is transmitted to the host system
either through the parallel or MIPI interface.
Figure 1 shows the major functional blocks of the
MT9D115.
Figure 1. MT9D155 Block Diagram
Sensor Core
Pixel Array
POR
Two-wire Serial IF
System Control
Image Flow Processor (IFP)
Color Pipeline
Stats Engine
Internal Register Bus
ROM Microcontroller SRAM
Microcontroller Unit (MCU)
Output Interface
FIFO
Formatter
MIPI
Parallel
MT9D115
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3
TYPICAL CONNECTION
1. This typical configuration shows only one scenario out of multiple possible variations for this sensor.
2. If a MIPI Interface is not required, the following pads must be left floating: D
OUT
_P, D
OUT
_N, CLK_P, and CLK_N.
3. The general purpose input/output (GPIO) pads can serve multiple features that can be reconfigured. The function and direction will vary
by applications.
4. Only one of the output modes (serial or parallel) can be used at any time.
5. ON Semiconductor recommends a resistor value of 1.5 kW to V
DD
_IO for the two-wire serial interface R
PULL-UP
; however, greater values
may be used for slower transmission speed.
6. V
AA
and V
AA
_PIX may be tied together. Although separate decoupling capacitors are recommended for V
AA
and V
AA
_PIX, decoupling
capacitors can be shared if one would like to reduce module size.
7. V
PP
is the one-time programmable memory (OTPM) programming voltage and should be left floating during normal operation.
8. 1.8 V supply shared by MIPI interface and V
DD
to reduce number of decoupling caps, hence, module size. V
DD
IO_TX must be connected
to a 1.8 V power supply source even though MIPI interface is not used.
9. ON Semiconductor recommends that 0.1 mF and 1 mF decoupling capacitors for each power supply are mounted as close as possible to
the pad and that a 10 mF capacitor be placed nearby off-module. Actual values and results may vary depending on layout and design
considerations. Please follow ON Semiconductor’s recommended capacitor Recommendations.
10.V
DD
_PLL and V
AA
can share the same power source in which case GND_PLL must be connected to GND.
11. Internal pull-up in RESET_BAR pin and can be left floating when not connected.
Figure 2. Typical Configuration (Connection)
I/O
Power
A
GND
S
CLK
S
DATA
V
DD
_IO
V
DD
_IO
Notes:
PIXCLK
V
DD
IO_TX/V
DD
V
AA
_PIX/
V
DD
_PLL/
V
AA
D
GND
GPIO[3:0]
3
EXTCLK
RESET_BAR
S
ADDR
Analog
Power
V
AA
_PIX
6
LINE_VALID
FRAME_VALID
D
OUT
[7:0]
CLK_N
CLK_P
To
Parallel
Camera
Port
To
Serial
Camera
Port
2
OR
4
R
PULL-Up
5
Slave
Two-wire
Serial
Interface
Active LOW Reset
External Clock In
(654 MHz)
General Purpose
I/Os (FLASH,
OE_BAR,
D
OUT
_LSB[1:0])
STANDBY
Standby Mode
GND_IO GND_PLL
V
AA
6
D
OUT
_N
D
OUT
_P
Digital
Core
Power
V
DD
PLL
Power
V
DD
_PLL
MIPI
Power
TX
V
DD
IO_TX
8
V
PP
7
0.1 mF0.1 mF0.1 mF

MT9D115D00STCK25AC1-200

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
INTEGRATED CIRCUIT
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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