MT9D115
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11
Integration Time
The integration time (exposure) of the MT9D115 is
controlled by variables. While coarse integration time
controls the integration duration in terms of row times, fine
integration time allows for sub-row times accuracy in terms
of pixel clocks. Integration time is updated in every frame by
the MCU auto feature. Disable the MCU auto features to
make manual adjustments to integration time.
Because of the basic operation of the Electronic Roller
Shutter (ERS), it is not advisable to set an integration time
that is greater than the frame time.
It is not necessary to reprogram the frame time on the
MT9D115 to make longer integration times available
because the frame time adjusts automatically. However,
long integration times increase the likelihood of image
degradation because of increased accumulation of dark
current.
If the integration time is changed while FV is asserted for
frame n, the first frame output using the new integration time
is frame (n + 2). The sequence is as follows:
1. During frame n, the new integration time is held in
the pending register.
2. At the start of frame (n + 1), the new integration
time is transferred to the live register. Integration
for each row of frame (n + 1) has been completed
using the old integration time.
3. The earliest time that a row can start integrating
using the new integration time is immediately after
that row has been read for frame (n + 1).
4. When frame (n + 2) is read out, it will have been
integrated using the new integration time.
If the integration time is changed on successive frames,
each value written will be applied for a single frame; the
latency between writing a value and it affecting the frame
readout remains at two frames.
When the integration time and the gain are changed at the
same time, the gain update is held off by one frame so that
the first frame output with the new integration time also has
the new gain applied.
External Generated Master Clock
If application does not use PLL, then the clock bypass bit
in R0x0014 must be set before exiting soft standby state as
follows:
1. Write 0x25F9 to R0x0014 to set clock bypass bit.
2. Delay min. of 100 ms.
3. Write 0x4028 to R0x0018 to exit from soft
standby state.
4. After successful exit from soft standby state,
disable the clock bypass bit by writing 0x21F9 to
R0x0014.
PLL-Generated Master Clock
The PLL can generate a master clock signal whose
frequency is up to 85 MHz (input clock from 6 MHz through
54 MHz).
PLL Setup
Because the input clock frequency is unknown, the sensor
starts up with the PLL disabled. The PLL takes time to power
up. During this time, the behavior of its output clock signal
is not guaranteed. The PLL output frequency is determined
by two constants, M and N, and the input clock frequency.
VCO +
F
in
2 M
N ) 1
(eq. 1)
PLL Output Frequency +
VCO
P1 ) 1
(eq. 2)
Digital Processing
Readout Options
The sensor core supports different readout options to
modify the image before it is sent to the IFP. The readout can
be limited to a specific window of the original pixel array.
For preview modes, the sensor core supports both
skipping and pixel averaging in x and y directions.
By changing the readout direction the image can be
flipped in the vertical direction and/or mirrored in the
horizontal direction.
Window Size
The image output size is set with registers x_addr_start,
x_addr_end, y_addr_start, and y_addr_end. The edge pixels
in the 1600 × 1200 array are present to avoid edge defects
and should not be included in the visible window. Binning
will change the image output size.
Readout Modes
Horizontal Mirror
When the sensor is configured to mirror the image
horizontally, the order of pixel readout within a row is
reversed, so that readout starts from x_addr_end and ends at
x_addr_start. Figure 10 shows a sequence of 6 pixels being
read out with normal readout and reverse readout. The SOC
corrects for this change in sensor core output.
