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MT9D115D00STCK25AC1-200

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
MT9D115
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40
Table 28. AC ELECTRICALS (continued)
(f
EXTCLK
= 6–54 MHz, V
DD
= V
DD
IO_TX = V
DD
_IO = 1.8 V; V
AA
= V
AA
_PIX = V
DD
_PLL = 2.8 V; T
j
= 25°C)
Symbol UnitMaxTypMinConditionParameter
Output Pin
Slew Rate
(Note 5)
Programmable Slew = 7
V
DD
_IO = 2.8 V, C
LOAD
= 45 pF − 1.6 − V/ns
V
DD
_IO = 1.8 V, C
LOAD
= 45 pF − 0.8 − V/ns
Programmable Slew = 4
V
DD
_IO = 2.8 V, C
LOAD
= 45 pF − 1.25 − V/ns
V
DD
_IO = 1.8 V, C
LOAD
= 45 pF − 0.55 − V/ns
Programmable Slew = 0
V
DD
_IO = 2.8 V, C
LOAD
= 45 pF − 0.3 − V/ns
V
DD
_IO = 1.8 V, C
LOAD
= 45 pF − 0.15 − V/ns
1. Measured when the PLL is off. Specification not applicable when PLL is on, but input HIGH/LOW voltage should be within specification.
2. V
IH
and V
IL
specifications apply to the over- and undershoot (ringing) present in the MCLK.
3. Measurement done with PLL off.
4. Valid for C
LOAD
< 20 pF on PIXCLK, D
OUT
[9:0], LINE_VALID, and FRAME_VALID pads. Loads must be matched as closely as possible.
5. PLL is off and EXTCLK is 24 MHz.
Table 29. DC ELECTRICALS
(f
EXTCLK
= 6–54 MHz, V
DD
= V
DD
IO_TX = V
DD
_IO = 1.8 V; V
AA
= V
AA
_PIX = V
DD
_PLL = 2.8 V; T
j
= 25°C, unless stated otherwise)
Symbol
Parameter Condition Min Typ Max Unit
V
DD
Digital Core Supply
Voltage
1.7 1.8 1.95 V
V
DD
_PLL PLL Supply Voltage 2.5 2.8 3.1 V
V
AA
Analog Supply Voltage 2.5 2.8 3.1 V
V
AA
_PIX Pixel Supply Voltage 2.5 2.8 3.1 V
V
DD
_IO Digital IO Supply
Voltage
For V
DD
_IO = 1.8 V 1.7 1.8 1.95 V
For V
DD
_IO = 2.8 V 2.5 2.8 3.1 V
V
DD
IO_TX MIPI Supply Voltage 1.7 1.8 1.95 V
V
PP
OTPM Supply Voltage − 8 − V
I
DD
_IO
(Note 1)
Digital IO Supply
Current
Context A
V
DD
_IO =1.8 V − 10 − mA
V
DD
_IO = 2.8 V − 15 − mA
Context B
V
DD
_IO = 1.8 V − 12 − mA
V
DD
_IO = 2.8 V − 20 − mA
I
DD
_PLL PLL Supply Current
PLL is OFF − N/A − mA
PLL is ON (Note 2) − 13 18 mA
I
DD
Digital Core Supply
Current
Operating in Parallel Mode Context A
− 15 30 mA
I
AA
Analog Supply Current − 40 50 mA
I
AA
_PIX Pixel Supply Current − 1.5 3 mA
IDDIO_TX MIPI Supply Current
(Note 3)
− N/A − mA
I
DD
Digital Core Supply
Current
Context B
− 25 52 mA
I
AA
Analog Supply Current − 40 52 mA
I
AA
_PIX Pixel Supply Current − 0.8 3 mA
I
DD
IO_TX MIPI Supply Current
(Note 3)
− N/A − mA
MT9D115
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41
Table 29. DC ELECTRICALS (continued)
(f
EXTCLK
= 6–54 MHz, V
DD
= V
DD
IO_TX = V
DD
_IO = 1.8 V; V
AA
= V
AA
_PIX = V
DD
_PLL = 2.8 V; T
j
= 25°C, unless stated otherwise)
Symbol UnitMaxTypMinConditionParameter
I
DD
Digital Core Supply
Current
Operating in Serial Mode
(Note 4)
Context A
− 23 50 mA
I
AA
Analog Supply Current − 40 50 mA
I
AA
_PIX Pixel Supply Current − 1.5 3 mA
I
DD
IO_TX MIPI Supply Current − 5 3 mA
I
DD
Digital Core Supply
Current
Context B
− 35 70 mA
I
AA
Analog Supply Current − 40 70 mA
I
AA
_PIX Pixel Supply Current − 0.8 3 mA
I
DD
IO_TX MIPI Supply Current − 8 10 mA
I
HARDSTANDBY
Total Standby Current
STANDBY Pin Asserted, R0x0028 = 1 (Note 5) − − 20
mA
I
HARDSTANDBY
STANDBY Pin Asserted, R0x0028 = 0 (Note 7) − − 90
mA
I
SOFTSTANDBY
R0x0018[0] = 1 (Note 6) − − 90
mA
I
SOFTSTANDBY
R0x0018[0] = 1, R0x0028 = 0 (Note 7) − − 2 mA
I
SOFTSTANDBY
R0x0018[0] = 1, R0x0028 = 1 (Note 7) − − 3 mA
1. V
DD
_IO current is dependent on the output data rate.
2. PLL is on with 85 MHz output frequency setting.
3. V
DD
_IO_TX current is only applicable in serial output mode.
4. PLL is on with 480 MHz VCO frequency settings.
5. Either with EXTCLK running or EXTCLK stopped and EXCLK pin is either pulled up or pulled down. Measured at T
j
= 70°C.
6. EXTCLK is stopped and EXCLK pin is either pulled up or pulled down.
7. EXTCLK running at 27 MHz.
MT9D115
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42
APPENDIX A − V
DD
_IO CURRENT ADDITION
Introduction
This appendix describes the system requirements to
achieve lowest power consumption in the V
DD
_IO domain
during low power hardware standby mode in
ON Semiconductor’s MT9D115 CMOS digital image
sensor.
V
DD
_IO Current
V
DD
_IO current is used to measure the power
consumption of the IO pad ring of our sensor. Therefore, it
is extremely system-dependent and greatly affected by the
external conditions as current can flow out of the chip
through the IO ring and into the system. In this document, we
outline requirements at the system level to achieve
minimum power consumption during low power hardware
standby mode.
To achieve the lowest V
DD
_IO current, it is critical to
match V
DD
_IO level in the sensor and the controller.
Otherwise, there can be elevated current drawn on the
V
DD
_IO due to mismatch in termination voltage level on the
sensor pins. In ON Semiconductor system design, the IO
voltage between the sensor and the controller is matched by
using the same voltage regulator, as shown in Figure 35.
This is recommended for both the system design and setup
to measure the V
DD
_IO power consumption.
Figure 35. Recommended System and Test Setup for Minimum V
DD
_IO Power Consumption
GND
Voltage
Regulator
Controller
MT9D115
2.2 kW
VIO_Controller
High-Z
High-Z
Drive HIGH
Drive LOW
Input
V
REG
V
DD
_IO
S
CLK
S
DATA
RESET_BAR,
STANDBY
S
ADDR
, EXTCLK
PIXCLK, FRAME_VALID,
LINE_VALID, D
OUT
[7:0],
GPIO[1:0]
GPIO[3:2]
GND
GND
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48

MT9D115D00STCK25AC1-200

Mfr. #:
Buy MT9D115D00STCK25AC1-200
Manufacturer:
ON Semiconductor
Description:
INTEGRATED CIRCUIT
Lifecycle:
New from this manufacturer.
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