MT9D115
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46
Figure 39. System Setup with Independent Voltage Sources for MT9D115 and Controller Chip
GND
Controller
VIO_Controller
High-Z
Drive HIGH
Drive LOW
V
REG1
V
DD
_IO
S
CLK
S
DATA
RESET_BAR, STANDBY
S
ADDR
, EXTCLK
PIXCLK, FRAME_VALID,
LINE_VALID, D
OUT
[7:0], GPIO[1:0]
GPIO[3:2]
GND
2.2 kW
Voltage
Regulator
Voltage
Regulator
V
REG2
GND
GND
Input
High-Z
DUT
MT9D115
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47
Test Sequence for Measuring V
DD
_IO Current
at Hard Standby Mode
Follow the procedure defined within the sensor data sheet.
The following test sequence takes the MT9D115 as
a reference. Contact your local ON Semiconductor
Applications Engineer for any specific product.
To measure V
DD
_IO current at hard standby mode:
1. Supply PWRDN (also known as STANDBY) pin
(J11 pin2) with 0 volt externally.
2. Supply the RESET_BAR pin (U22 pin4) with
V
DD
_IO volt externally.
3. Connect an ammeter between I
DD
_IO (J9) and
D
GND
.
4. Use jumpers J5, J17, and J20 to make sure GPIO
pins are connected to either GND or V
DD
_IO.
At this point, the part is in operating mode and it is
possible to load an .INI file to get an image with
DevWare.
5. Supply the PWRDN pin with V
DD
_IO volt
externally and wait for one frame + 50 clock. At
this stage, the part is in hard standby.
6. By removing J1, the EXTCLK is disconnected to
the part and then connect EXTCLK pin (J1 pin2)
to either D
GND
or V
DD
_IO.
7. Now the part is in hard standby with EXTCLK off.
The user can read off the V
DD
_IO current from the
ammeter at step 3 above.
Figure 40. Modifications to the Demo2 Sensor Head Board for V
DD
_IO Current Measurement
Modifications
J9 jumper removed to monitor IDDIO
by connecting Ammeter on Pins 1
and 2
To control the Reset pin externally,
U22 was removed and a 10 kW
resistor connected to Pin 4, which is
connected to a 2.8 V external source
J11 jumper removed to control the
STANDBY or PWDN pin externally.
A 10K resistor is connected for pull
up on this pin. in 2 in operating= 0 V,
Hard Standby= 2.8 V using external
voltage source.
J1 jumper for CLOCK
Conclusion
It is important from the system perspective to ensure IO
levels between MT9D115 and the controller chip at the same
potential level to achieve minimum IO power consumption
in MT9D115. A system configuration to achieve this is
proposed in this document. In addition, suggestions on how
to approach system designs with multiple two-wire serial
interface devices and multiple IO level devices are provided.
MT9D115
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48
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