OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

MT9D115D00STCK25AC1-200

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
MT9D115
www.onsemi.com
43
IO Pin States
In addition to matching V
DD
_IO levels between the
controller chip and the sensor, the control signals to the input
pins of the sensor must be at a specified level to achieve
minimal V
DD
_IO current draw. Table 30 shows the pin
states recommended to achieve minimum V
DD
_IO current
during hardware standby mode.
It is always a good practice to measure the pin voltage
during hard standby and try to match the recommended pin
state.
Table 30. STATUS OF SIGNALS DURING STANDBY STATE
Signal State on Sensor Pin ON Semiconductor Test System
D
OUT
[7:0] High-Z by Default (configurable through OE_BAR or two-wire serial
interface register)
No Control
(Note 4)
PIXCLK High-Z by Default (configurable)
LINE_VALID High-Z by Default (configurable)
FRAME_VALID High-Z by Default (configurable)
GPIO[3:0] Depending on how the system uses them as
D
OUT
_LSB1/D
OUT
_LSB0/FLASH/OE_BAR
Pulled to GND
(Note 8, 9)
D
OUT
_N 0
Float
(Note 7)
D
OUT
_P 0
CLK_N 0
CLK_P 0
S
ADDR
Input
Pulled to GND
(Note 1, 6)
EXTCLK Input
S
DATA
Input
High-Z
(Note 3)
S
CLK
Input
RESET_BAR Input
Pulled to V
DD
_IO Level
(Notes 2, 5)
STANDBY Input
1. V
IL
specification for input signal applies. Refer to Table 21, “GPIO Related Registers and Variables”.
2. V
IH
specification for input signal applies. Refer to Table 21, “GPIO Related Registers and Variables”.
3. These pins are not directly connected to V
DD
_IO supply but through a voltage follower to the controller.
4. The pins on the controller connected to these sensor pins are input pins.
5. These pins are not directly connected to V
DD
_IO supply but through the controller.
6. These pins are not directly connected to GND but through the control signal on the controller.
7. These pins are floating in parallel mode operation.
8. Tie all the unused GPIO pins to D
GND
or V
DD
_IO level in the module.
9. If GPIO3 is connected to GPIO pin on the controller, program GPIO3 as an input before low power hard standby mode and drive GPIO3
externally from the controller to D
GND
level.
RESET_BAR with Internal Pull-Up
The RESET_BAR pin has an internal pull-up device to
V
DD
_IO (see Figure 36).
Figure 36. RESET_BAR Pad Architecture
VDDIO
RESET_BAR Pad
Block Diagram
HysteresisRx
Z
Pad
R
PULLUP
MT9D115
www.onsemi.com
44
Since R
PULLUP
is active devices connected in triode state,
the value of R
PULLUP
is dependent on the difference
between V
DD
_IO and V
PAD
Level (see Table 31).
Table 31. TYPICAL MISMATCH CURRENT IN V
DD
_IO DUE TO MISMATCH IN RESET_BAR LEVEL AND V
DD
_IO LEVEL
(Conditions: V
DD
= V
DD
_IO_TX = 1.8 V; V
AA
= V
AA
_PIX = V
DD
_PLL = 2.8 V; T
j
=30°C, EXTCLK is off and tied to GND level. All other pin
states and levels are set according to ON Semiconductor E2E on pin states.)
V
DD
_IO V
PAD
Min Typ Max Unit
1.80
1.70 14 18 22 mA
1.80 2 5 10
1.95 –13 –17 –21
2.80
2.50 61 67 72
2.80 2 7 12
3.10 –54 –60 –66
NOTE: The above data is for engineering purposes only. These represent typical values that can be expected.
Recommended System and Test Setup with Multiple
Serial Interface Slave Devices
The recommended system and test setup shown in
Figure 37 is only valid for a system where MT9D115 is the
only two-wire serial interface slave device connected to the
controller chip. As the S
CLK
and S
DATA
are to be pulled high
to the V
DD
_IO level during the hardware standby to
minimize the IO current consumption due to the data
toggling in the two-wire serial interface, this design is not
feasible if there is an additional slave device sharing the
same two-wire serial interface on the controller chip.
In such systems, it is recommended to have a voltage
follower to isolate the pull-up resistors attached between the
two-wire serial interface and V
DD
_IO supply of MT9D115
as shown in Figure 37. Otherwise, the data toggling from the
two-wire serial interface transactions to other could cause
leakage from the V
DD
_IO supply of MT9D115.
Figure 37. Recommended System and Test Setup for Minimum V
DD
_IO Power Consumption in the MT9D115
Sharing with Multiple Two-wire Serial Interface Devices
GND
Voltage
Regulator
Controller
MT9D115
VIO_Controller
X
X
Drive HIGH
Drive LOW
Input
V
REG
V
DD
_IO
S
CLK
S
DATA
RESET_BAR,
STANDBY
S
ADDR
, EXTCLK
PIXCLK, FRAME_VALID,
LINE_VALID, D
OUT
[7:0],
GPIO[1:0]
GPIO[3:2]
GND
GND
Voltage
Follower
Other Slave Devices
MT9D115
www.onsemi.com
45
In addition, in some system designs where the IO level of
the additional devices sharing the same two-wire serial
interface with MT9D115 is different from that of MT9D115,
it is recommended that the IO voltage level between the
controller and the MT9D115 be maintained to the same level
by sourcing from the same voltage regular as shown in
Figure 38.
Figure 38. Recommended System and Test Setup for Minimum V
DD
_IO Power Consumption in the MT9D115
Sharing with Multiple Two-wire Serial Interface Devices at Different IO Level
GND
Voltage
Regulator
Controller
MT9D115
VIO_Controller
X
X
Drive HIGH
Drive LOW
Input
V
REG1
V
DD
_IO
S
CLK
S
DATA
RESET_BAR,
STANDBY
S
ADDR
, EXTCLK
PIXCLK, FRAME_VALID,
LINE_VALID, D
OUT
[7:0],
GPIO[1:0]
GPIO[3:2]
GND
GND
Voltage
Follower
Other Slave Devices
Voltage
Regulator
V
REG2
For a system which uses separate voltage regulators for
MT9D115 sensor and the controller chip as shown in
Figure 39, it is important to match the voltage levels
between two regulators as close as possible. If the voltage
levels are not matched, there can be additional current
consumption in the V
DD
_IO domain connected to the
sensor. This additional current is generated in the internal
pull up resistor present in RESET_BAR pad and external
resistors used for two-wire serial interface.
The current leakage from the voltage level mismatch in
RESET_BAR pad can be characterized as follows:
I
DD
_IOmismatch +
V
REG2
* V
REG1
R
PULLUP
RESET_BAR@V
DD
_IO
(eq. 19)
The internal pull up resistance is dependent on the
V
DD
_IO level. Typical levels of mismatch current at
different V
DD
_IO levels can be found in Table 31.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48

MT9D115D00STCK25AC1-200

Mfr. #:
Buy MT9D115D00STCK25AC1-200
Manufacturer:
ON Semiconductor
Description:
INTEGRATED CIRCUIT
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet