MT9D115
www.onsemi.com
9
Always-On Power Domain
The always-on power domain (AOPD) provides an area
of functionality that will always be active while power is
applied to the MT9D115. The external host interface is
located in the AOPD. The domain also includes
miscellaneous clock and reset controls as well as
configuration registers for the sensor core, processor core,
clock configuration, and clock reset control. The
user-loadable patch memory is also included in this domain.
This memory will remain powered when the main core
power is shut down using the standby command.
Sensor Core
The sensor core of the MT9D115 is a progressive-scan
sensor that generates a stream of pixel data at a constant
frame rate, qualified by LINE_VALID (LV) and
FRAME_VALID (FV). The maximum pixel rate is 30 Mp/s,
corresponding to a pixel clock rate of 63.25 MHz. See
Figure 7 for a block diagram of the sensor core. It includes
a 2.0 Mp active-pixel array. The timing and control circuitry
sequences through the rows of the array, resetting and then
reading each row in turn. In the time interval between
resetting a row and reading that row, the pixels in the row
integrate incident light. The exposure is controlled by
varying the time interval between reset and readout. After
a row is read, data from the columns are sequenced through
an analog signal chain that provides offset correction and
gain, and then through an ADC. The output from the ADC
is a 10-bit value for each pixel in the array.
The pixel array contains optically active and
light-shielded (dark) pixels. The dark pixels provide data for
the offset-correction algorithms (black level control).
The sensor core contains a set of control and status
registers that can be used to control many aspects of the
sensor behavior including the frame size, exposure, and gain
settings. These registers are controlled by the firmware and
can be accessed through a two-wire serial interface. Register
values written to the sensor core can be overwritten by
firmware.
The output from the core is a Bayer pattern, where
alternate rows are a sequence of either green and red pixels
or blue and green pixels. The offset and gain stages of the
analog signal chain provide per-color control of the pixel
data.
A flash strobe output signal is provided to allow an
external xenon or LED light source to synchronize with the
sensor exposure time.
Figure 7. Sensor Core Block Diagram
Sensor Core
Sensor ( APS )
Array
Timing
and
Control
Control Registers
Gr and Gb
Channel
Red and Blue
Channel
Analog
Processing
ADC
PLL
Digital
Processing
10-bit
Data Out
Gr and Gb
Red and Blue
Gr and Gb
Red and Blue
Active-pixel
