MT9D115D00STCK25AC1-200 Datasheet MT9D115D00STCK25AC1-200 | P16-P18

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Figure 18. Pixel Readout (x_odd_inc = 3, y_odd_inc = 3, xy_bin = 1)

X Incrementing

Y Incrementing

Binning Limitations

Binning requires a different sequencing of the pixel array

and imposes different timing limits on the operation of the

sensor. In particular, xy-binning requires two READ

operations from the pixel array for each line of output data,

which has the effect of increasing the minimum line

blanking time.

As a result, when xy-binning is enabled, some of the

programming limits declared in the parameter limit registers

are no longer valid. In addition, the default values for some

of the manufacturer-specific registers need to be

reprogrammed. None of these adjustments are required for

x-binning. The sensor must be taken out of streaming mode

before switching between binned and non-binned operation.

The row addresses for various binning modes are shown in

Table 7.

Table 7. ROW ADDRESS SEQUENCING (BINNING)

Normal

Binning Sequence 1 Binning Sequence 2

0 0, 2 No Data

1 1, 3 No Data

2 No Data 2, 4

3 No Data 3, 5

4 4, 6 No Data

5 5, 7 No Data

6 No Data 6, 8

7 No Data 7, 9

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Raw Data Format

The sensor core image data is read out in a progressive

scan. Valid image data is surrounded by horizontal blanking

and vertical blanking, (see Figure 19). The amount of

horizontal blanking and vertical blanking is programmable.

LV is HIGH during the shaded region of the figure.

Figure 19. Valid Image Data

0,0

0,1

0,2

… P

0,0

0,n

0,1

1,1

2,1

… P

1,n−1

1,n

m−1,0

m−1,1

m−1,2

… P

m−1,n−1

m−1,n

m,0

m,1

m,2

… P

m,n−1

m,n

Valid Image Horizontal Blanking

Vertical/Horizontal

Blanking

Vertical Blanking

00 00 00 …

00 00 00

……

00 00 00 …

00 00 00

00 00 00 … 00 00 00

Raw Data Timing

The sensor core output data is synchronized with the

PIXCLK output. When LV is HIGH, one pixel’s data is

output on the 10-bit D

OUT

output bus every PIXCLK period.

By default, the PIXCLK signal runs at the same frequency

as the master clock, and its falling edges occur one-half of

a master clock period after transitions on LV, FV, and

OUT

[9:0] (see Figure 20). This allows PIXCLK to be used

as a clock to sample the data. PIXCLK is continuously

enabled, even during the blanking period.

Figure 20. Pixel Data Timing Example

LINE_VALID

PIXCLK

OUT

0−D

OUT

(9:0)

n−1

(9:0)

Valid Image DataBlanking Blanking

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Input Interface to Image Flow Processor

The input interface to the IFP is the front end of the IFP,

in which it will choose between the sensor core output or

a test pattern generator output. During normal operation,

a stream of raw Bayer image data from the sensor is

continuously fed into the IFP. For testing purposes, the test

generator output is selected. The generator provides

a selection of test patterns sufficient for basic testing of the

IFP. Program variable (ID = 7, Offset = 0x66) followed by

REFRESH command to the sequencer in order to access

different test patterns (see Table 8).

Depending on which test pattern has been selected, the

user might need to program additional registers in order to

see the intended effects.

Table 8. AVAILABLE TEST PATTERNS

Test Pattern Registers/Variables Example

Flat Field mode_common

settings_test_mode

(ID = 7, Offset = 0x66) = 1

test_pxl_red (R0x0102) = 0x1ff

test_pxl_g1 (R0x0104) = 0x1ff

test_pxl_g2 (R0x0106) = 0x1ff

test_pxl_blue (R0x0108) = 0x1ff

Vertical Ramp mode_common_

mode_settings

test_mode

(ID = 7, Offset = 0x66) = 2

Color Bar mode_common_

mode_settings

test_mode

(ID = 7, Offset = 0x66) = 3

Vertical Stripes mode_common

settings_test_mode

(ID = 7, Offset = 0x66) = 4

test_pxl_red (R0x0102) = 0x1ff

test_pxl_g1 (R0x0104) = 0x17d

test_pxl_g2 (R0x0106) = 0x000

test_pxl_blue (R0x0108) = 0x000

Pseudo-Random mode_common_mode

settings_test_mode

(ID = 7, Offset = 0x66) = 5

Horizontal Stripes mode_common

settings_test_mode

(ID = 7, Offset = 0x66) = 6

test_pxl_red (R0x0102) = 0x1ff

test_pxl_g1 (R0x0104) = 0x17d

test_pxl_g2 (R0x0106) = 0x000

test_pxl_blue (R0x0108) = 0x000

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MT9D115D00STCK25AC1-200

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