GS1532 Data Sheet
21498 - 8 February 2007 28 of 51
The timing of these signals is shown in Figure 3-2.
Figure 3-2: H, V, F Timing
H:V:F TIMING - HD 20-BIT INPUT MODE
PCLK
LUMA DATA OUT
CHROMA DATA OUT
H
XYZ
(eav)
0000003FF
XYZ
(eav)
0000003FF
V
F
XYZ
(sav)
0000003FF
XYZ
(sav)
0000003FF
H;V:F TIMING AT SAV - HD 10-BIT INPUT MODE
0000003FF3FF
XYZ
(sav)
000000
XYZ
(sav)
PCLK
H
V
F
H:V:F TIMING AT EAV - HD 10-BIT INPUT MODE
PCLK
0000003FF3FF
XYZ
(eav)
000000
XYZ
(eav)
MULTIPLEXED
Y/Cr/Cb DATA OUT
H
V
F
MULTIPLEXED
Y/Cr/Cb DATA OUT
H:V:F TIMING - SD 20-BIT INPUT MODE
PCLK
CHROMA DATA OUT
LUMA DATA OUT
H
0003FF
XYZ
(eav)
000
V
F
0003FF
XYZ
(SAV)
000
H:V:F TIMING - SD 10-BIT INPUT MODE
MULTIPLEXED
Y/Cr/Cb DATA OUT
PCLK
H
V
F
XYZ
(eav)
0000003FF
XYZ
(sav)
0000003FF
H SIGNAL TIMING:
H_CONFIG = LOW
H_CONFIG = HIGH
GS1532 Data Sheet
21498 - 8 February 2007 29 of 51
3.4 DVB-ASI mode
The GS1532 is said to be in DVB-ASI mode when the SMPTE_BYPASS pin is set
LOW and the DVB_ASI and SD/HD
pins are set HIGH.
In this mode, all SMPTE processing functions are disabled, and the 8-bit transport
stream data will be 8b/10b encoded prior to serialization.
3.4.1 Control Signal Inputs
In DVB-ASI mode, the DIN19 and DIN18 pins will be configured as DVB-ASI
control signals INSSYNCIN and KIN respectively.
When INSSYNCIN is set HIGH, the device will insert K28.5 sync characters into
the data stream. This function is used to assist system implementations where the
GS1532 may be preceded by an external data FIFO. Parallel DVB-ASI data may
be clocked into the FIFO at some rate less than 27MHz. The INSSYNCIN input
may then be connected to the FIFO empty signal, thus providing a means of
padding up the data transmission rate to 27MHz. See Figure 3-3.
NOTE: 8b/10b encoding will take place after K28.5 sync character insertion.
KIN should be set HIGH whenever the parallel data input is to be interpreted as any
special character defined by the DVB-ASI standard (including the K28.5 sync
character). This pin should be set LOW when the input is to be interpreted as data.
NOTE: When operating in DVB-ASI mode, DIN[9:0] become high impedance.
Figure 3-3: DVB-ASI FIFO Implementation using the GS1532
3.5 Data-Through Mode
The GS1532 may be configured by the application layer to operate as a simple
parallel-to-serial converter. In this mode, the device presents data to the output
buffer without performing any scrambling or encoding.
Data-through mode is enabled only when both the SMPTE_BYPASS
and
DVB_ASI pins are set LOW.
8
8
AIN ~ HIN
PCLK = 27MHz
INSSYNCIN
SD
O
CLK_IN
CLK_OUT
FIFO
SD
O
W
RITE_CLK
<
27MHz
FE
TS
KIN
GS1532
KIN
READ CLK
=27MHz
GS1532 Data Sheet
21498 - 8 February 2007 30 of 51
3.6 Additional Processing Functions
The GS1532 contains an additional data processing block which is available in
SMPTE mode only, (see SMPTE Mode on page 27).
3.6.1 Input Data Blank
The video input data may be 'blanked' by the GS1532. In this mode, all input video
data except TRS words are set to the appropriate blanking levels by the device.
Both the horizontal and vertical ancillary data spaces will also be set to blanking
levels.
This function is enabled by setting the BLANK
pin LOW.
3.6.2 Automatic Video Standard Detection
The GS1532 can detect the input video standard by using the timing parameters
extracted from the received TRS ID words or supplied H, V, and F timing signals
(see Internal Flywheel on page 27). This information is presented to the host
interface via the VIDEO_STANDARD register (Table 3-2).
Total samples per line, active samples per line, total lines per field/frame and active
lines per field/frame are also calculated and presented to the host interface via the
RASTER_STRUCTURE registers (Table 3-3). These line and sample count
registers are updated once per frame at the end of line 12. This is in addition to the
information contained in the VIDEO_STANDARD register.
After device reset, the four RASTER_STRUCTURE registers default to zero.
Table 3-2: Host Interface Description for Video Standard Register
Register Name Bit Name Description R/W Default
VIDEO_STANDARD
Address: 004h
15 Not Used.
14-10 VD_STD[4:0] Video Data Standard (see Table 3-4). R 0
9 INT_PROG
Interlace/Progressive: Set LOW if detected video
standard is PROGRESSIVE and is set HIGH if it is
INTERLACED.
R0
8 STD_LOCK Standard Lock: Set HIGH when flywheel has
achieved full synchronization.
R0
7-0 Not Used.

GS1532-CFE3

Mfr. #:
Manufacturer:
Semtech
Description:
Serializers & Deserializers - Serdes LQFP-80pin
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New from this manufacturer.
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