GS1532 Data Sheet
21498 - 8 February 2007 46 of 51
Alternatively, if the test capabilities are to be used in the system, the host may still
control the JTAG/HOST
input signal, but some means for tri-stating the host must
exist in order to use the interface at ATE. This is represented in Figure 3-12.
Figure 3-12: System JTAG
Please contact your Gennum representative to obtain the BSDL model for the
GS1532.
3.12 Device Power Up
The GS1532 has a recommended power supply sequence. To ensure correct
power up, power the CORE_VDD pins before the IO_VDD pins.
Device pins may also be driven prior to power up without causing damage.
To ensure that all internal registers are cleared upon power-up, the application
layer must hold the
RESET_TRST signal LOW for a minimum of 1ms after the core
power supply has reached the minimum level specified in the DC Electrical
Characteristics Table, (Table 2-1). See Figure 3-13.
3.13 Device Reset
In order to initialize all internal operating conditions to their default states the
application layer must hold the
RESET_TRST signal LOW for a minimum of t
reset
=
1ms.
When held in reset, all device outputs will be driven to a high-impedance state.
Figure 3-13: Reset Pulse
GS1532
CS_TMS
SCLK_TCK
SDIN_TDI
SDOUT_TDO
JTAG_HOST
In-circuit ATE probe
Tri-State
CORE_VDD
ESET_TRST
treset
+1.65V
+1.8V
Reset
Reset
treset
