GS1532 Data Sheet
21498 - 8 February 2007 37 of 51
FF_LINE_START_F0
Address: 016h
15-10 Not Used.
9-0 FF_LINE_START_F0[9:0] Field 0 Full Field start line data used to set EDH
calculation range outside of RP 165 values.
R/W 0
FF_LINE_END_F0
Address: 017h
15-10 Not Used.
9-0 FF_LINE_END_F0[9:0] Field 0 Full Field end line data used to set EDH
calculation range outside of RP 165 values.
R/W 0
FF_LINE_START_F1
Address: 018h
15-10 Not Used.
9-0 FF_LINE_START_F1[9:0] Field 1 Full Field start line data used to set EDH
calculation range outside of RP-165 values.
R/W 0
FF_LINE_END_F1
Address: 019h
15-10 Not Used.
9-0 FF_LINE_END_F1[9:0] Field 1 Full Field end line data used to set EDH
calculation range outside of RP-165 values.
R/W 0
Table 3-8: Host Interface Description for EDH Calculation Range Registers (Continued)
Register Name Bit Name Description R/W Default
Table 3-9: Host Interface Description for EDH Flag Register
Register Name Bit Name Description R/W Default
EDH_FLAG
Address: 002h
15 Not Used.
14 ANC-UES Ancillary Unknown Error Status flag will be
generated and inserted when IOPROC_EN/DIS
and
SMPTE_BYPASS
pins are HIGH and
EDH_CRC_INS bit is LOW. SD mode only.
R/W 0
13 ANC-IDA Ancillary Internal device error Detected Already flag
will be generated and inserted when
IOPROC_EN/DIS
and SMPTE_BYPASS pins are
HIGH and EDH_CRC_INS bit is LOW. SD mode
only.
R/W 0
12 ANC-IDH Ancillary Internal device error Detected Here flag
will be generated and inserted when
IOPROC_EN/DIS
and SMPTE_BYPASS pins are
HIGH and EDH_CRC_INS bit is LOW. SD mode
only.
R/W 0
11 ANC-EDA Ancillary Error Detected Already flag will be
generated and inserted when IOPROC_EN/DIS
and
SMPTE_BYPASS
pins are HIGH and
EDH_CRC_INS bit is LOW. SD mode only.
R/W 0
10 ANC-EDH Ancillary Error Detected Here flag will be generated
and inserted when IOPROC_EN/DIS
and
SMPTE_BYPASS
pins are HIGH and
EDH_CRC_INS bit is LOW. SD mode only.
R/W 0
9 FF-UES Full Field Unknown Error flag will be generated and
inserted when IOPROC_EN/DIS
and
SMPTE_BYPASS
pins are HIGH and
EDH_CRC_INS bit is LOW. SD mode only.
R/W 0
GS1532 Data Sheet
21498 - 8 February 2007 38 of 51
8 FF-IDA Full Field Internal device error Detected Already flag
will be generated and inserted when
IOPROC_EN/DIS
and SMPTE_BYPASS pins are
HIGH and EDH_CRC_INS bit is LOW. SD mode
only.
R/W 0
7 FF-IDH Full Field Internal device error Detected flag will be
generated and inserted when IOPROC_EN/DIS
and
SMPTE_BYPASS
pins are HIGH and
EDH_CRC_INS bit is LOW. SD mode only.
R/W 0
6 FF-EDA Full Field Error Detected Already flag will be
generated and inserted when IOPROC_EN/DIS
and
SMPTE_BYPASS
pins are HIGH and
EDH_CRC_INS bit is LOW. SD mode only.
R/W 0
5 FF-EDH Full Field Error Detected Here flag will be generated
and inserted when IOPROC_EN/DIS
and
SMPTE_BYPASS
pins are HIGH and
EDH_CRC_INS bit is LOW. SD mode only.
R/W 0
4 AP-UES Active Picture Unknown Error Status flag will be
generated and inserted when IOPROC_EN/DIS
and
SMPTE_BYPASS
pins are HIGH and
EDH_CRC_INS bit is LOW. SD mode only.
R/W 0
3 AP-IDA Active Picture Internal device error Detected
Already flag will be generated and inserted when
IOPROC_EN/DIS
and SMPTE_BYPASS pins are
HIGH and EDH_CRC_INS bit is LOW. SD mode
only.
R/W 0
2 AP-IDH Active Picture Internal device error Detected Here
flag will be generated and inserted when
IOPROC_EN/DIS
and SMPTE_BYPASS pins are
HIGH and EDH_CRC_INS bit is LOW. SD mode
only.
R/W 0
1 AP-EDA Active Picture Error Detected Already flag will be
generated and inserted when IOPROC_EN/DIS
and
SMPTE_BYPASS
pins are HIGH and
EDH_CRC_INS bit is LOW. SD mode only.
R/W 0
0 AP-EDH Active Picture Error Detected Here flag will be
generated and inserted when IOPROC_EN/DIS
and
SMPTE_BYPASS
pins are HIGH and
EDH_CRC_INS bit is LOW. SD mode only.
R/W 0
Table 3-9: Host Interface Description for EDH Flag Register (Continued)
Register Name Bit Name Description R/W Default
GS1532 Data Sheet
21498 - 8 February 2007 39 of 51
3.6.3.4 Ancillary Data Checksum Generation and Insertion
The GS1532 will calculate checksums for all detected ancillary data packets
presented to the device. These calculated checksum values are inserted into the
data stream prior to serialization.
Ancillary data checksum generation and insertion will only take place if the
ANC_CSUM_INS bit of the IOPROC_DISABLE register is set LOW.
3.6.3.5 Line Based CRC Generation and Insertion
The GS1532 will generate and insert line based CRC words into both the Y and C
channels of the data stream. This feature is only available in HD mode and is
enabled by setting the CRC_INS bit of the IOPROC_DISABLE register LOW.
3.6.3.6 HD Line Number Generation and Insertion
In HD mode, the GS1532 will calculate and insert line numbers into the Y and C
channels of the output data stream.
Line number generation is in accordance with the relevant HD video standard as
determined by the device, (see Automatic Video Standard Detection on page 30).
This feature is enabled when SD/HD
= LOW, and the LNUM_INS bit of the
IOPROC_DISABLE register is set LOW.
3.6.3.7 TRS Generation and Insertion
The GS1532 can generate and insert 10-bit TRS code words into the data stream
as required. This feature is enabled by setting the TRS_INS bit of the
IOPROC_DISABLE register LOW.
TRS word generation will be performed in accordance with the timing parameters
generated by the flywheel which will be locked either to the received TRS ID words
or the supplied H, V, and F timing signals (see Internal Flywheel on page 27).
3.7 Parallel-To-Serial Conversion
The parallel data output of the internal data processing blocks is fed to the
parallel-to-serial converter. The function of this block is to generate a serial data
stream from the 10-bit or 20-bit parallel data words and pass the stream to the
integrated cable driver.

GS1532-CFE3

Mfr. #:
Manufacturer:
Semtech
Description:
Serializers & Deserializers - Serdes LQFP-80pin
Lifecycle:
New from this manufacturer.
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