GS1532-CFE3 Datasheet GS1532-CFE3 | P43-P45

GS1532 Data Sheet

21498 - 8 February 2007 43 of 51

When operating in GSPI mode, the SCLK, SDIN, and CS signals are provided by

the host interface. The SDOUT pin is a high-impedance output allowing multiple

devices to be connected in parallel and selected via the CS

input. The interface is

illustrated in the Figure 3-6 below.

All read or write access to the GS1532 is initiated and terminated by the host

processor. Each access always begins with a 16-bit command word on SDIN

indicating the address of the register of interest. This is followed by a 16-bit data

word on SDIN in write mode, or a 16-bit data word on SDOUT in read mode.

Figure 3-6: Gennum Serial Peripheral Interface (GSPI)

3.10.1 Command Word Description

The command word is transmitted MSB first and contains a read/write bit, nine

reserved bits and a 6-bit register address. Set R/W = '1' to read and R/W = '0' to

write from the GSPI.

Command words are clocked into the GS1532 on the rising edge of the serial clock

SCLK. The appropriate chip select signal, CS

, must be asserted low a minimum of

1.5ns (t

in Figure 3-9 and Figure 3-10) before the first clock edge to ensure proper

operation.

Each command word must be followed by only one data word to ensure proper

operation.

Figure 3-7: Command Word

Figure 3-8: Data Word

SCLK

SDOUT

SDIN

SCLK

SDIN

SDOUT

Application Host

GS1532

R/W RSV RSV RSV A0A1A2A3A4A5RSVRSVRSVRSVRSV RSV

MSB

LSB

D15 D14 D13 D12 D0D1D2

D3D4

D6D7

D11 D10

MSB

GS1532 Data Sheet

21498 - 8 February 2007 44 of 51

3.10.2 Data Read and Write Timing

Read and write mode timing for the GSPI interface is shown in Figure 3-9 and

Figure 3-10 respectively. The maximum SCLK frequency allowed is 6.6MHz.

When writing to the registers via the GSPI, the MSB of the data word may be

presented to SDIN immediately following the falling edge of the LSB of the

command word. All SDIN data is sampled on the rising edge of SCLK.

When reading from the registers via the GSPI, the MSB of the data word will be

available on SDOUT 12ns (t

) following the falling edge of the LSB of the command

word, and thus may be read by the host on the very next rising edge of the clock.

The remaining bits are clocked out by the GS1532 on the negative edges of SCLK.

Figure 3-9: GSPI Read Mode Timing

Figure 3-10: GSPI Write Mode Timing

3.10.3 Configuration and Status Registers

Table 3-11 summarizes the GS1532's internal status and configuration registers.

All of these registers are available to the host via the GSPI and are all individually

addressable.

Where status registers contain less than the full 16 bits of information, two or more

registers may be combined at a single logical address.

DOUT

R/W

RSV

A0A1

A2A3

RSV

RSVRSV

D15 D14 D13 D12

D4D5

D11

D10

SCLK

SDIN

RSV

input data

setup time

duty

cycle

period

output data

hold time

R/W

RSV

A0A1

A2A3

RSV

RSVRSV

D15 D14 D13 D12

D4D5

D11

D10

SCLK

DIN

RSV

input data

setup time

duty

cycle

period

GS1532 Data Sheet

21498 - 8 February 2007 45 of 51

3.11 JTAG

When the JTAG/HOST input pin of the GS1532 is set HIGH, the host interface port

will be configured for JTAG test operation. In this mode, pins 27 through 30

become TMS, TDO, TDI, and TCK. In addition, the RESET_TRST

pin will operate

as the test reset pin.

Boundary scan testing using the JTAG interface will be enabled in this mode.

There are two methods in which JTAG can be used on the GS1532:

1. As a stand-alone JTAG interface to be used at in-circuit ATE (Automatic Test

Equipment) during PCB assembly; or

2. Under control of the host for applications such as system power on self tests.

When the JTAG tests are applied by ATE, care must be taken to disable any other

devices driving the digital I/O pins. If the tests are to be applied only at ATE, this

can be accomplished with tri-state buffers used in conjunction with the

JTAG/HOST

input signal. This is shown in Figure 3-11.

Figure 3-11: In-Circuit JTAG

Table 3-11: GS1532 Internal Registers

Address Register Name See Section

000h IOPROC_DISABLE Section 3.6.3

002h EDH_FLAG Section 3.6.3.3

004h VIDEO_STANDARD Section 3.6.2

00Ah - 00Bh VIDEO_FORMAT Section 3.6.3.1

00Eh - 011h RASTER_STRUCTURE Section 3.6.2

012h - 019h EDH_CALC_RANGES Section 3.6.3.3

01Bh - 01Ch LINE_352M Section 3.6.3.1

Application HOST

GS1532

CS_TMS

SCLK_TCK

SDIN_TDI

SDOUT_TDO

JTAG_HOST

In-circuit ATE probe

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GS1532-CFE3

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