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GS1532-CFE3

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51
GS1532 Data Sheet
21498 - 8 February 2007 31 of 51
3.6.2.1 Video Standard Indication
The video standard codes reported in the VD_STD[4:0] bits of the
VIDEO_STANDARD register represent the SMPTE standards as shown in
Table 3-4.
In addition to the 5-bit video standard code word, the VIDEO_STANDARD register
also contains two status bits. The STD_LOCK bit will be set HIGH whenever the
flywheel has achieved full synchronization. The INT_PROG
bit will be set LOW if
the detected video standard is progressive and HIGH if the detected video
standard is interlaced.
The VD_STD[4:0], STD_LOCK and INT_PROG
bits of the VIDEO_STANDARD
register will default to zero after device reset. The VD_STD[4:0] and INT_PROG
bits will also default to zero if the SMPTE_BYPASS
pin is asserted LOW or if the
LOCKED output is LOW. The STD_LOCK bit will retain its previous value if the
PCLK is removed.
Table 3-3: Host Interface Description for Raster Structure Registers
Register Name Bit Name Description R/W Default
RASTER_STRUCTURE1
Address: 00Eh
15-12 – Not Used. – –
11-0 RASTER_STRUCTURE_1[11:0] Words Per Active Line R 0
RASTER_STRUCTURE2
Address: 00Fh
15-12 – Not Used. – –
11-0 RASTER_STRUCTURE_2[11:0] Words Per Total Line. R 0
RASTER_STRUCTURE3
Address: 010h
15-11 – Not Used. – –
10-0 RASTER_STRUCTURE_3[10:0] Total Lines Per Frame R 0
RASTER_STRUCTURE4
Address: 011h
15-11 – Not Used. – –
10-0 RASTER_STRUCTURE_4[10:0] Active Lines Per Field R 0
Table 3-4: Supported Video Standards
VD_STD[4:0] SMPTE
Standard
Video Format Length of
HANC
Length of
Active Video
Total
Samples
SMPTE352M
Lines
00h 296M (HD) 1280x720/60 (1:1) 358 1280 1650 13
01h 296M (HD) 1280x720/60 (1:1) - EM 198 1440 1650 13
02h 296M (HD) 1280x720/30 (1:1) 2008 1280 3300 13
03h 296M (HD) 1280x720/30 (1:1) - EM 408 2880 3300 13
04h 296M (HD) 1280x720/50 (1:1) 688 1280 1980 13
05h 296M (HD) 1280x720/50 (1:1) - EM 240 1728 1980 13
06h 296M (HD) 1280x720/25 (1:1) 2668 1280 3960 13
07h 296M (HD) 1280x720/25 (1:1) - EM 492 3456 3960 13
08h 296M (HD) 1280x720/24 (1:1) 2833 1280 4125 13
GS1532 Data Sheet
21498 - 8 February 2007 32 of 51
3.6.3 Packet Generation and Insertion
In addition to input data blanking and automatic video standards detection, the
GS1532 may also calculate, assemble and insert into the data stream various
types of ancillary data packets and TRS ID words.
09h 296M (HD) 1280x720/24 (1:1) - EM 513 3600 4125 13
0Ah 274M (HD) 1920x1080/60 (2:1) or
1920x1080/30 (PsF)
268 1920 2200 10, 572
0Bh 274M (HD) 1920x1080/30 (1:1) 268 1920 2200 18
0Ch 274M (HD) 1920x1080/50 (2:1) or
1920x1080/25 (PsF)
708 1920 2640 10, 572
0Dh 274M (HD) 1920x1080/25 (1:1) 708 1920 2640 18
0Eh 274M (HD) 1920x1080/25 (1:1) - EM 324 2304 2640 18
0Fh 274M (HD) 1920x1080/25 (PsF) - EM 324 2304 2640 10, 572
10h 274M (HD) 1920x1080/24 (1:1) 818 1920 2750 18
11h 274M (HD) 1920x1080/24 (PsF) 818 1920 2750 10, 572
12h 274M (HD) 1920x1080/24 (1:1) - EM 338 2400 2750 18
13h 274M (HD) 1920x1080/24 (PsF) - EM 338 2400 2750 10, 572
14h 295M (HD) 1920x1080/50 (2:1) 444 1920 2376 10, 572
15h 260M (HD) 1920x1035/60 (2:1) 268 1920 2200 10, 572
16h 125M (SD) 1440x487/60 (2:1)
(Or dual link progressive)
268 1440 1716 3, 276
17h 125M (SD) 1440x507/60 (2:1) 268 1440 1716 3, 276
19h 125M (SD) 525-line 487 generic – – 1716 3, 276
1Bh 125M (SD) 525-line 507 generic – – 1716 3, 276
18h ITU-R BT.656
(SD)
1440x576/50 (2:1)
(Or dual link progressive)
280 1440 1728 9, 322
1Ah ITU-R BT.656
(SD)
625-line generic (EM) – – 1728 9, 322
1Dh Unknown HD – – – – –
1Eh Unknown SD – – – – –
1Ch, 1Fh Reserved – – – – –
NOTE: Though the GS1532 will work correctly on and serialize both 59.94Hz and 60Hz formats, it will not distinguish between them.
Table 3-4: Supported Video Standards (Continued)
VD_STD[4:0] SMPTE
Standard
Video Format Length of
HANC
Length of
Active Video
Total
Samples
SMPTE352M
Lines
GS1532 Data Sheet
21498 - 8 February 2007 33 of 51
These features are only available when the device is set to operated in SMPTE
mode and the IOPROC_EN/DIS
pin is set HIGH. Individual insertion features may
be enabled or disabled via the IOPROC_DISABLE register (Table 3-5).
All of the IOPROC_DISABLE register bits default to '0' after device reset, enabling
all of the processing features. To disable any individual error correction feature, the
host interface must set the corresponding bit HIGH in this register.
Table 3-5: Host Interface Description for Internal Processing Disable Register
Register Name Bit Name Description R/W Default
IOPROC_DISABLE
Address: 000h
15-9 – Not Used. – –
8 H_CONFIG Horizontal sync timing input configuration. Set LOW
when the H input timing is based on active line
blanking (default). Set HIGH when the H input
timing is based on the H bit of the TRS words. See
Figure 3-2.
R/W 0
7 – Not Used. – –
6 352M_INS SMPTE352M packet insertion. In HD mode, 352M
packets are inserted in the Y channel only when one
of the bytes in the VIDEO_FORMAT_A or
VIDEO_FORMAT_B registers are programmed with
non-zero values. The IOPROC_EN/DIS
pin and
SMPTE_BYPASS
pin must also be set HIGH. Set
HIGH to disable.
R/W 0
5 ILLEGAL_REMAP Illegal Code Remapping. Detection and correction
of illegal code words within the active picture area
(AP). The IOPROC_EN/DIS
pin and
SMPTE_BYPASS
pin must also be set HIGH. Set
HIGH to disable.
R/W 0
4 EDH_CRC_INS Error Detection & Handling (EDH) Cyclical
Redundancy Check (CRC) error correction. In SD
mode the GS1532 will generate and insert EDH
packets. The IOPROC_EN/DIS
pin and
SMPTE_BYPASS
pin must also be set HIGH. Set
HIGH to disable.
R/W 0
3 ANC_CSUM_INS Ancillary Data Checksum insertion. The
IOPROC_EN/DIS
pin and SMPTE_BYPASS pin
must also be set HIGH. Set HIGH to disable.
R/W 0
2 CRC_INS Y and C line-based CRC insertion. In HD mode,
line-based CRC words are inserted in both the Y
and C channels. The IOPROC_EN/DIS
pin and
SMPTE_BYPASS
pin must be also set HIGH. Set
HIGH to disable
R/W 0
1 LNUM_INS Y and C line number insertion - HD mode only. The
IOPROC_EN/DIS
pin and SMPTE_BYPASS pin
must be set HIGH. Set HIGH to disable.
R/W 0
0 TRS_INS Timing Reference Signal Insertion. Occurs only
when IOPROC_EN/DIS
is HIGH and
SMPTE_BYPASS
is HIGH. Set HIGH to disable.
R/W 0
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51

GS1532-CFE3

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Buy GS1532-CFE3
Manufacturer:
Semtech
Description:
Serializers & Deserializers - Serdes LQFP-80pin
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