NCP1855
www.onsemi.com
12
System
awake
Figure 7. Typical Charging Profile of NCP1855 with System Awake
V
SAFE
V
PRE
V
RECHG
V
BAT
V
CHG
V
BAT
I
BAT
I
SYS
I
BAT
I
SAFE
I
EOC
I
PRE
I
CHG
Safe
Charge
Pre
Charge
Constant
Current
Constant
Voltage
End of
Charge
I
CHG
current is programmable using I2C interface
(register IBAT_SET − bits ICHG[3:0] and ICHG_HIGH).
Constant Voltage (full charge):
The constant voltage phase is also a part of the full charge
state. When the battery voltage is close to its maximum
(V
CHG
), the charge circuit will transition from a constant
current to a constant voltage mode where the charge current
will slowly decrease (taper off). The battery is now voltage
controlled. V
CHG
voltage is programmable using I2C
interface (register VBAT_SET− bits CTRL_VBAT[5:0]).
End of Charge:
The charge is completed (end of charge state) when the
battery is above the V
RECHG
threshold and the charge current
below the I
EOC
level. The battery is considered fully charged
and the battery charge is halted. Charging is resumed in the
constant current phase when the battery voltage drops below
the V
RECHG
threshold. I
EOC
current is programmable using
I2C interface (register IBAT_SET− bits IEOC[2:0]).
Power Stage Control
NCP1855 provides a fully−integrated 1.5 MHz
step−down DC−DC converter for high efficiency. For an
optimized charge control, 3 feedback signals control the
PWM duty cycle. These 3 loops are: maximum input current
(I
INLIM
), maximum charge current (I
CHG
) and, maximum
charge voltage (V
CHG
). The switcher is regulated by the first
loop that reaches its corresponding threshold. Typically
during charge current phase (V
PRE
< V
BAT
< V
RECHG
), the
measured input current and output voltage are below the
programmed limit and asking for more power. But in the
same time, the measured output current is at the
programmed limit and thus regulates the DC−DC converter.
In order to prevent battery discharge and overvoltage
protection, Q1 (reverse voltage protection) and Q2 (high
side N−MOSFET of the DC−DC converter) are mounted in
a back−to−back common drain structure while Q3 is the low
side N MOSFET of the DC−DC converter. Q2 gate driver
circuitry required an external bootstrap capacitor connected
between CBOOT pin and SW pin.
An internal current sense monitors and limits the
maximum allowable current in the inductor to I
PEAK
value.
Charger Detection, Start−up Sequence and System Off
The start−up sequence begins upon an adaptor valid
voltage plug in detection: V
IN
> V
INDET
and V
IN
− V
BAT
>
V
CHGDET
(off state).
Then, the internal circuitry is powered up and the presence
of BATFET is reported (register STATUS – bit BATFET).
When the power−up sequence is done, the charge cycle is
automatically launched. At any time and any state, the user
can hold the charge process and transit to fault state by
setting CHG_EN to ‘0’ (register CTRL1) in the I
2
C register.
The I2C registers are accessible without valid voltage on
V
IN
if V
CAP
> V
SYSUV
(i.e. if V
BAT
is higher than V
SYSUV
+ voltage drop across Q2 body diode).
At any time, the user can reset all register stacks (register
CTRL1 – bit REG_RST).
Weak Battery Support
An optional battery FET (Q
BAT
) can be placed between
the application and the battery. In this way, the battery can
be isolated from the application and so−called weak battery
operation is supported.
