NCP1855
www.onsemi.com
16
Charge Status Reporting
FLAG pin
FLAG pin is used to report charge status to the system
processor and for interruption request.
During charger active states and wait state, the pin FLAG
is low in order to indicate that the charge of the battery is in
progress. When charge is completed or disabled or a fault
occurs, the FLAG pin is high as the charge is halted.
STATUS and CONTROL Registers
The status register contains the current charge state,
BATFET connection as well as fault and status interrupt
(bits FAULTINT and STATINT in register STATUS). The
charge state (bits STATE in register STATUS) is updated on
the fly and corresponds to the charging state described in
Charging process section. An interruption (see description
below) is generated upon a state change. In the config state,
hardware detection is performed on BAFTET pins. From
wait state, their statuses are available (bit BATFET in
register STATUS). STATINT bit is set to 1 if an interruption
appears on STAT_INT register (see description below).
FAULTINT bit is set to 1 if an interruption appears on
registers CH1_INT, CH1_INT or BST_INT. Thanks to this
register, the system controller knows the chip status with
only one I
2
C read operation. If a fault appears or a status
change (STATINT bits and FAULTINT), the controller can
read corresponding registers for more details.
Interruption
Upon a state or status change, the system controller is
informed by sensing FLAG pin. A T
FLAGON
pulse is
generated on this pin in order to signalize an event. The level
of this pulse depends on the state of the charger (see
Charging process section):
• When charger is in charger active states and wait state
the FLAG is low and consequently the pulse level on
FLAG pin is high.
• In the other states, the pulse level is low as the FLAG
stable level is high.
Charge state transition even and all bits of register
STAT_INT, CH1_INT, CH2_INT, BST_INT generate an
interrupt request on FLAG pin and can be masked with the
corresponding mask bits in registers STAT_MSK,
CH1_MSK, CH2_MSK and BST_MSK. All interrupt
signals can be masked with the global interrupt mask bit (bit
INT_MASK register CTRL1). All these bits are read to
clear. The register map (see REGISTERS MAP section)
indicated the active transition of each bits (column “TYPE”
in REGISTERS MAP section).
If more than 1 interrupt appears, only 1 pulse is generated
while interrupt registers (STAT_INT, CH1_INT, CH2_INT,
BST_INT) will not fully clear.
Sense and Status Registers
At any time the system processor can know the status of
all the comparators inside the chip by reading VIN_SNS,
VBAT_SNS, and TEMP_SNS registers (read only). These
bits give to the system controller the real time values of all
the corresponding comparators outputs (see BLOCK
DIAGRAM).
Battery Removal
During normal charge operation the battery may bounce
or be removed. The state transition of the state machine only
occurs upon deglitched signals which allow bridging any
battery bounce. True battery removal will last longer than
the debounce times. The NCP1855 handles battery removal
if a BATFET is present and power path option is enable
(register CRTL2 bit PWR_PATH=1)
If the battery removal appears during the charge cycle, the
NCP1855 will behave normally and charge up very quickly
the equivalent capacitor seen on VSENSN and/or VBAT
(from tens to hundreds of milliseconds). The state machine
will automatically end up in end of charge / dpp state while
the DCDC is still enabled and the system still supplied.
Factory Mode and No Battery Operation
During factory testing no battery is present in the
application and a supply could be applied through the
bottom connector to power the application. The state
machine will support this mode of operation if a BATFET is
present and if the application processor can configure
NCP1855 within 32 seconds. In factory mode condition, the
NCP1855 is locked in weak wait state (DCDC enable and no
weak charge). The factory mode is enabled through the
FTRY pin or through I
2
C (Register CTRL1 Bit
FCTRY_MOD_REG) according to the following logic
table.
FTRY Pin FCTRY_MOD_REG
FTRY_MODE
(Factory mode)
0 0 Enable
0 1 Disable
1 0 Disable
1 1 Enable
Remark: The charge current loop (ICHG) and input current
loop are disabled in factory mode so full power is available
for the system.
Through I
2
C the device is entirely programmable so the
controller can configure appropriate current and voltage
threshold to handle factory testing.
