NCP1855
www.onsemi.com
14
Weak Charge Exit
In some application cases, the system may not be able to
start in weak charge states due to current capability
limitation or/and configuration of the system. If so, in order
to avoid unexpected “drop and retry” sequence of the buck
output, the charge state machine allows only 3 system
power−up sequences based on SPM pin level: If SPM pin
level is toggled 3 times during weak charge states, the
system goes directly to safe charge state and a full charge
mode sequence is initiated (“Power fail” condition in
Charging process section).
Power Path Management
Power path management can be supported when a battery
FET (Q
BAT
) is placed between the application and the
battery. When the battery is fully charged (end of charge
state), power path management disconnects the battery from
the system by opening Q
BAT
, while the DC−DC remains
active. This will keep the battery in a fully charged state with
the system being supplied from the DC−DC. If a load
transient appears exceeding the DC−DC output current and
thus causing V
SENSEN
to fall below V
RECHG
, the FET Q
BAT
is instantaneously closed to reconnect the battery in order to
provide enough current to the application. The FET Q
BAT
remains closed until the end of charge state conditions are
reached again. The power path management function is
enabled through the I
2
C interface (register CRTL2 bit
PWR_PATH=1).
Safety Timer Description
The safety timer ensures proper and safe operation during
charge process. The set and reset condition of the different
safety timer (Watchdog timer, Charge timer, Wakeup timer
and USB timer) are detailed below. When a timer expires
(condition “timeout” in Charging process section), the
charge process is halted.
Watchdog Timer
Watchdog timer ensures software remains alive once it
has programmed the IC. The watchdog timer is no longer
running since I
2
C interface is not available. Upon an I
2
C
write, automatically a watchdog timer T
WD
is started. The
watchdog timer is running during charger active states and
fault state. Another I
2
C write will reset the watchdog timer.
When the watchdog times out, the state machine reverts to
fault state and reported through I
2
C interface (register
CHINT2– bit WDTO). Also used to time out the fault state.
This timer can be disabled (Register CTRL2 bit
WDTO_DIS).
Charge Timer
A charge timer T
CHG
is running that will make that the
overall charge to the battery will not exceed a certain amount
of energy. The charge timer is running during charger active
states and halted during charger not active states (see
Charging process section). The timer can also be cleared any
time through I
2
C (register CTRL1 – bit TCHG_RST). The
state machine transitions to fault state when the timer
expires. This timer can be disabled (Register CTRL2 bit
CHGTO_DIS).
USB Timer
A USB charge timer T
USB
is running in the charger active
states while halted in the charger non active states. The timer
keeps running as long as the lowest input current limit
remains selected either by ILIM pin or I
2
C (register I_SET
– bit IINLIM and IINLIM_EN and register IINLIM_SET
bits IINLIM_TA). This will avoid exceeding the maximum
allowed USB charge time for un−configured connections.
When expiring, the state machine will transition to fault
state. The timer is cleared in the off state or by I
2
C command
(register CTRL1 – bit TCHG_RST).
Wake up Timer
Before entering weak charge state, NCP1855 verifies if
the input current available is enough to supply both the
application and the charge of the battery. A wake−up timer
T
WU
verifies if ILIM pin is raised fast enough or application
powered up (by monitoring register I_SET – bit IINLIM and
IINLIM_EN and register IINLIM_SET bits IINLIM_TA)
after a USB attachment. The wake up timer is running in
weak wait state and weak safe state and clears when the input
current limit is higher than 100 mA.
Input Current Limitation
In order to be USB specification compliant, the input
current at V
IN
is monitored and could be limited to the
I
INLIM
threshold. The input current limit threshold is
selectable through the ILIMx pin. When low, the one unit
USB current is selected (I
IN
≤ 100 mA), where when made
high 5 units are selected (I
IN
≤ 500 mA). In addition, this
current limit can be programmed through I
2
C (register
MISC_SET bits IINLIM and register IINLIM_SET bits
IINLIM_TA) therefore defeating the state of the ILIMx pin.
In case of non−limited input source, current limit can be
disabled (register CTRL2 bit IINLIM_EN). The current
limit is valid within operating input voltage range (V
INDET
< V
IN
< V
INOV
).
