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NCP1855FCCT1G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
NCP1855
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22
Table 5. REGISTERS MAP
Bit Function
RST
Value
NameResetType
CH1_MSK REGISTER − Memory location : 0B
7−5
R No_Reset RESERVED 0
4 RW OFF STATE, POR,
REG_RST, OTGMODE
VINLO_MASK 0 VINLO interruption mask bit.
3 RW OFF STATE, POR,
REG_RST, OTGMODE
VINHI_MASK 0 VINHI interruption mask bit.
2 R No_Reset RESERVED 0
1 RW OFF STATE, POR,
REG_RST, OTGMODE
BUCKOVP_MASK 0 BUCKOVP interruption mask bit.
0 RW OFF STATE, POR,
REG_RST, OTGMODE
STATECHG_MASK 0 State transition interruption mask bit.
CH2_MSK REGISTER − Memory location : 0C
7−4
R No_Reset RESERVED 0000
3 RW OFF STATE, POR,
REG_RST, OTGMODE
WDTO_MASK 1 WDTO interruption mask bit.
2 RW OFF STATE, POR,
REG_RST, OTGMODE
USBTO_MASK 1 USBTO interruption mask bit.
1 RW OFF STATE, POR,
REG_RST, OTGMODE
CHGTO_MASK 1 CHGTO interruption mask bit.
0 R No_Reset RESERVED 0
BST_MSK REGISTER − Memory location : 0D
7−5
R No_Reset RESERVED 0
4 RW OFF STATE, POR,
REG_RST, OTGMODE
VOBSTOL2_MASK 1
3 RW OFF STATE, POR,
REG_RST, OTGMODE
VOBSTOL1_MASK 1
2 RW OFF STATE, POR,
REG_RST, OTGMODE
VBUSOV_MASK 1
1 RW OFF STATE, POR,
REG_RST, OTGMODE
VBAT_NOK_MASK 1
0 RW OFF STATE, POR,
REG_RST, OTGMODE
STATEOTG_MASK 1 STATEOTG interruption mask bit.
VBAT_SET REGISTER − Memory location : 0E
7−6
R No_Reset RESERVED 00
5−0 RW OFF STATE, POR,
REG_RST, OTGMODE
CTRL_VBAT [5:0] 001100 000000: 3.3 V
001100: 3.6 V
110000: 4.5 V
Step: 0.025 V
IBAT_SET REGISTER − Memory location : 0F
7
RW OFF STATE, POR,
REG_RST, OTGMODE
ICHG_HIGH 0 Output current MSB:
0, ICHG[] = ICHG
1, ICHG[] = 1.6A + ICHG
6−4 RW OFF STATE, POR,
REG_RST, OTGMODE
IEOC[2:0] 010 000: 100 mA
010: 150 mA
111: 275 mA
Step: 25 mA
3−0 RW OFF STATE, POR,
REG_RST, OTGMODE
ICHG[3:0] 0110 Output range current programmable range:
0000: 450 mA
1111: 1.9 A
Step: 100 mA
NCP1855
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23
Table 5. REGISTERS MAP
Bit Function
RST
Value
NameResetType
MISC_SET REGISTER − Memory location : 10
7
R Reserved
6−5 RW OFF STATE, POR,
REG_RST, OTGMODE
IWEAK[1:0] 01 Charge current during weak battery states:
00: Disable
01: 100 mA
10: 200 mA
11: 300 mA
4−2 RW OFF STATE, POR,
REG_RST, OTGMODE
CTRL_VFET[2:0] 011 Battery to system re−connection threshold:
000: 3.1 V
001: 3.2 V
010: 3.3 V
011: 3.4 V
100: 3.5 V
101: 3.6 V
1−0 RW OFF STATE, POR,
REG_RST, OTGMODE
IINLIM[2:0] 00 Input current limit range:
00: 100 mA
01: 500 mA
10: 900 mA
11: 1500 mA
IINLIM_SET REGISTER − Memory location : 11
7−4
RW OFF STATE, POR,
REG_RST, OTGMODE
IINLIM_TA[3:0] 0000 Input current limit range:
0000: IINLIM
0001: 600 mA
1111: 2000 mA
Step: 100 mA
NCP1855
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24
Application Information
Bill of Material
IN
FLAG
SCL
SDA
SPM
TRANS
CAP
BAT
FET
WEAK
SENSN
SENSP
CBOOT
SW
USB PHY
ILIM1
AGND
PGND
OTG
+
NCP1855
CORE
SYSTEM
VBUS
D+
D−
ID
GND
C
IN
C
CAP
C
CORE
C
TRS
C
BOOT
C
OUT
R
SNS
L
X
4.7
μF
2.2
μF
1
μF
0.1
μF
10 nF
2.2
μH
33mW
22
μF
Q
BAT
(*)
ILIM2
FTRY
Figure 10. Typical Application Example
Item Part Description Ref Value PCB Footprint Manufacturer Manufacturer Reference
1 Ceramic Capacitor 25 V X5R C
IN
1 mF
0603 MURATA GRM188R61E105K
2 Ceramic Capacitor 25 V X5R C
CAP
4.7 mF
0805 MURATA GRM21BR61E475KA12L
3 Ceramic Capacitor 6.3 V X5R C
CORE
2.2 mF
0402 MURATA GRM155R60J225M
4 Ceramic Capacitor 6.3 V X5R C
TRS
0.1 mF
0402 MURATA GRM155R60J104K
5 Ceramic Capacitor 10 V X5R C
BOOT
10 nF 0402 MURATA GRM155R60J103K
6 Ceramic Capacitor 6.3 V X5R C
OUT
22 mF
0603 MURATA GRM31CR60J226K
7 SMD Inductor L
X
2.2 mH
3012 TDK SPM3012T-2R2M
8 SMD Resistor 0.25 W, 1% R
SNS
33 mW
0805 YAGEO RL0805FR-7W0R033L
9 Power channel P-MOSFET Q
BAT
18 mW
UDFN 2*2mm ONSEMI NTLUS3A18PZ
PCB Layout Consideration
Particular attention must be paid with C
CORE
capacitor as
it’s decoupling the supply of internal circuitry including gate
driver. This capacitor must be placed between CORE pin
and PGND pin with a minimum track length.
The high speed operation of the NCP1855 demands
careful attention to board layout and component placement.
To prevent electromagnetic interference (EMI) problems,
attention should be paid specially with components L
X
,
C
CAP
, and C
OUT
as they constitute a high frequency current
loop area. The power input capacitor C
CAP
, connected from
CAP to PGND, should be placed as close as possible to the
NCP1851. The output inductor L
X
and the output capacitor
C
OUT
connected between R
SNS
and PGND should be placed
close to the IC. C
IN
capacitor should also be place as close
as possible to IN and PGND pin as well.
The high current charge path through IN, CAP, SW,
inductor L1, Resistor R1, optional BAFTET, and battery
pack must be sized appropriately for the maximum charge
current in order to avoid voltage drops in these traces. An
IWEAK current can flow through WEAK and BAT traces
witch defines the appropriate track width.
It’s suggested to keep as complete ground plane under
NCP1854 as possible. PGND and AGND pin connection
must be connected to the ground plane.
Care should be taken to avoid noise interference between
PGND and AGND. Finally it is always good practice to keep
the sensitive tracks such as feedbacks connections (SENSP,
SENSN, BAT) away from switching signal connections by
laying the tracks on the other side or inner layer of PCB.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

NCP1855FCCT1G

Mfr. #:
Buy NCP1855FCCT1G
Manufacturer:
ON Semiconductor
Description:
Battery Management 2.5A SWITCHING BATTERY CH
Lifecycle:
New from this manufacturer.
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