PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
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DD4C8_16_32x64AG.fm - Rev. B 9/04 EN
1 ©2004 Micron Technology, Inc.
64MB, 128MB, 256MB (x64, SR)
184-PIN DDR SDRAM UDIMM
DDR SDRAM
DIMM
MT4VDDT864A – 64MB
MT4VDDT1664A – 128MB
MT4VDDT3264A – 256MB
For the latest data sheet, please refer to the Micron
Web
site: www.micron.com/products/modules
Features
• JEDEC standard 184-pin, unbuffered dual in-line
memory module (DDR DIMM)
• Utilizes 266 MT/s and 333MT/s DDR SDRAM
components
• Fast data transfer rates: PC2100 or PC2700
• 64MB (8 Meg x 64), 128MB (16 Meg x 64), and
256MB (32 Meg x 64)
•V
DD= VDDQ= +2.5V
•V
DDSPD = +2.3V to +3.6V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/
received with data—i.e., source-synchronous data
capture
• Differential clock inputs (CK and CK#)
• Four internal device banks for concurrent operation
• Selectable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes: 15.625µs
(64MB); 7.8125µs (128MB, 256MB) maximum
average periodic refresh interval.
• Serial Presence Detect (SPD) with EEPROM
• Selectable READ CAS latency for maximum
compatibility
•Gold edge contacts
Figure 1: 184-Pin DIMM (MO–206)
NOTE: 1. Consult Micron for product availability.
2. CL = Device CAS (READ) Latency.
OPTIONS MARKING
• Operating Temperature Range
Commercial (0°C to +70°C) None
Industrial (-40°C to +85°C)
1
I
•Package
184-pin DIMM (Standard) G
184-Pin DIMM (Lead-free)
1
Y
• Memory Clock, Speed, CAS Latency
2
6ns, 333 MT/s (167 MHz), CL = 2.5 -335
7.5ns, 266 MT/s (133 MHz), CL = 2 -262
1
7.5ns, 266 MT/s (133 MHz), CL = 2 -26A
1
7.5ns, 266 MT/s (133 MHz), CL = 2.5
-265
•PCB
1.25in. (31.75mm) See page 2 note
Table 1: Address Table
64MB 128MB 256MB
Refresh Count
4K 8K 8K
Row Addressing
4K (A0–A11) 8K(A0–A12) 8K(A0–A12)
Device Bank Addressing
4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)
Device Configuration
128Mb (8 Meg x 16) 256Mb (16 Meg x 16) 512Mb (32 Meg x 16)
Column Addressing
512 (A0–A8) 512 (A0–A8) 1K (A0–A9)
Module Rank Addressing
1 (S0#) 1 (S0#) 1 (S0#)