64MB, 128MB, 256MB (x64, SR)
184-PIN DDR SDRAM UDIMM
pdf: 09005aef8085081a, source: 09005aef806e129d Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD4C8_16_32x64AG.fm - Rev. B 9/04 EN
5 ©2004 Micron Technology, Inc.
27, 29, 32, 37, 41, 43,
48, 115 (128MB, 256MB), 118,
122, 125, 130, 141
A0–A11
(64MB)
A0–A12
(128MB, 256MB)
Input
Address Inputs: Provide the row address for ACTIVE
commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines
whether the PRECHARGE applies to one device bank (A10
LOW, device bank selected by BA0, BA1) or all device banks
(A10 HIGH). The address inputs also provide the op-code
during a MODE REGISTER SET command. BA0 and BA1 define
which mode register (mode register or extended mode
register) is loaded during the LOAD MODE REGISTER
command.
91 SDA Input/
Output
Serial Presence-Detect Data: SDA is a bidirectional pin used
to transfer addresses and data into and out of the presence-
detect portion of the module.
92 SCL Input
Serial Clock for Presence-Detect: SCL is used to synchronize
the presence-detect data transfer to and from the module.
181, 182, 183 SA0–SA2 Input
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
97, 107, 119, 129, 149, 159,
169, 177
DM0–DM7 Input/
Output
Data Write Mask: DM LOW allows WRITE operation. DM
HIGH blocks WRITE operation. DM lines do not affect READ
operation.
5, 14, 25, 36, 56, 67, 78, 86 DQS0–DQS7 Input/
Output
Data Strobe: Output with READ data, input with WRITE data.
DQS is edge-aligned with READ data, centered in WRITE
data. Used to capture data.
2, 4, 6, 8, 12, 13, 19, 20, 23, 24,
28, 31, 33, 35, 39, 40, 53, 55,
57, 60, 61, 64, 68, 69, 72, 73,
79, 80, 83, 84, 87, 88, 94, 95,
98, 99, 105, 106, 109, 110, 114,
117, 121, 123, 126, 127, 131,
133, 146, 147, 150, 151, 153,
155, 161, 162, 165, 166, 170,
171, 174, 175, 178, 179
DQ0–DQ63 Input/
Output
Data I/Os: Data bus.
1V
REF Supply
SSTL_2 reference voltage.
15, 22, 30, 54, 62, 77, 96, 104,
112, 128, 136, 143, 156, 164,
172, 180
V
DDQ Supply
DQ Power Supply: +2.5V ±0.2V.
7, 38, 46, 70, 85, 108, 120, 148,
168
VDD Supply
Power Supply: +2.5V ±0.2V.
3, 11, 18, 26, 34, 42, 50, 58, 66,
74, 81, 89, 93, 100, 116, 124,
132, 139, 145, 152, 160, 176
V
SS Supply
Ground.
184 V
DDSPD Supply
Serial EEPROM positive power supply: +2.3V to +3.6V.
9, 71, 82, 90, 101, 102, 103,
113, 115 (64MB), 158, 163, 167,
173
NC –
No Connect: These pins should be left unconnected.
10, 44, 45, 47, 49, 51, 111, 134,
135, 140, 142, 144
DNU –
Do Not Use: These pins are not connected on this module but
are assigned pins on other modules in this product family.
Table 5: Pin Descriptions
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information
PIN NUMBERS SYMBOL TYPE DESCRIPTION
