64MB, 128MB, 256MB (x64, SR)
184-PIN DDR SDRAM UDIMM
pdf: 09005aef8085081a, source: 09005aef806e129d Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD4C8_16_32x64AG.fm - Rev. B 9/04 EN
7 ©2004 Micron Technology, Inc.
General Description
The MT4VDDT864A, MT4VDDT1664A, and
MT4VDDT3264A are high-speed CMOS, dynamic ran-
dom-access, 64MB, 128MB, and 256MB memory mod-
ules organized in a x64 configuration. DDR SDRAM
modules use internally configured quad-bank DDR
SDRAM devices.
DDR SDRAM modules use a double data rate archi-
tecture to achieve high-speed operation. The double
data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two
data words per clock cycle at the I/O pins. A single
read or write access for DDR SDRAM modules effec-
tively consists of a single 2n-bit wide, one-clock-cycle
data transfer at the internal DRAM core and two corre-
sponding n-bit wide, one-half-clock-cycle data trans-
fers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at
the receiver. DQS is an intermittent strobe transmitted
by the DDR SDRAM during READs and by the memory
controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for
WRITEs.
DDR SDRAM modules operate from differential
clocks (CK, CK#); the crossing of CK going HIGH and
CK# going LOW will be referred to as the positive edge
of CK. Commands (address and control signals) are
registered at every positive edge of CK. Input data is
registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both
edges of CK.
Read and write accesses to DDR SDRAM modules
are burst oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with the
registration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the device bank and row to be
accessed (BA0, BA1 select device bank, A0–A11 (64MB)
or A0–A12 (128MB, 256MB) select device row). The
address bits registered coincident with the READ or
WRITE command are used to select the device bank
and the starting device column location for the burst
access.
DDR SDRAM modules provide for programmable
read or write burst lengths of 2, 4, or 8 locations. An
auto precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end of
the burst access.
The pipelined, multibank architecture of DDR
SDRAM modules allows for concurrent operation,
thereby providing high effective bandwidth by hiding
row precharge and activation time.
An auto refresh mode is provided, along with a
power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All out-
puts are SSTL_2, Class II compatible. For more
information regarding DDR SDRAM operation, refer to
the 128Mb, 256Mb, or 512Mb DDR SDRAM compo-
nent data sheets.
Serial Presence-Detect Operation
DDR SDRAM modules incorporate serial presence-
detect (SPD). The SPD function is implemented using
a 2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes can be pro-
grammed by Micron to identify the module type and
various SDRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for
use by the customer. System READ/WRITE operations
between the master (system logic) and the slave
EEPROM device (DIMM) occur via a standard I
2
C bus
using the DIMM’s SCL (clock) and SDA (data) signals,
together with SA (2:0), which provide eight unique
DIMM/EEPROM addresses. Write protect (WP) is tied
to ground on the module, permanently disabling hard-
ware write protect.
Mode Register Definition
The mode register is used to define the specific
mode of operation of DDR SDRAM devices. This defi-
nition includes the selection of a burst length, a burst
type, a CAS latency and an operating mode, as shown
in Figure 3, Mode Register Definition Diagram, on
page 8. The mode register is programmed via the
MODE REGISTER SET command (with BA0 = 0 and
BA1 = 0) and will retain the stored information until it
is programmed again or the device loses power (except
for bit A8, which is self-clearing).
Reprogramming the mode register will not alter the
contents of the memory, provided it is performed cor-
rectly. The mode register must be loaded (reloaded)
when all device banks are idle and no bursts are in
progress, and the controller must wait the specified
time before initiating the subsequent operation. Vio-
lating either of these requirements will result in
unspecified operation.
Mode register bits A0–A2 specify the burst length,
A3 specifies the type of burst (sequential or inter-
leaved), A4–A6 specify the CAS latency, and A7–A11
(64MB), or A7–A12 (128MB, 256MB) specify the oper-
ating mode.
