64MB, 128MB, 256MB (x64, SR)
184-PIN DDR SDRAM UDIMM
pdf: 09005aef8085081a, source: 09005aef806e129d Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD4C8_16_32x64AG.fm - Rev. B 9/04 EN
15 ©2004 Micron Technology, Inc.
Table 14: IDD Specifications and Conditions – 256MB
DDR SDRAM components only
Notes: 1–5, 8, 10, 12, 48; notes appear on pages 18–21; 0°C ≤ T
A
≤ +70°C; VDD = VDDQ = +2.5V ±0.2V
MAX
PARAMETER/CONDITION SYM -335 -262
-26A/
-265 UNITS NOTES
OPERATING CURRENT: One device bank; Active-Precharge;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing once
per clock cycle; Address and control inputs changing once every
two clock cycles.
I
DD0 520 520 460 mA 20, 42
OPERATING CURRENT: One device bank; Active-Read-Precharge;
Burst = 4;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); IOUT = 0mA; Address
and control inputs changing once per clock cycle.
I
DD1 640 640 580 mA 20, 42
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks
idle; Power-down mode;
t
CK =
t
CK (MIN); CKE = LOW.
I
DD2P 20 20 20 mA 21, 28,
44
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;
t
CK =
t
CK (MIN); CKE = HIGH; Address and other control inputs changing
once per clock cycle. V
IN = VREF for DQ, DQS, and DM.
IDD2F 180 180 160 mA 45
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank
active; Power-down mode;
t
CK =
t
CK (MIN); CKE = LOW.
I
DD3P 140 140 120 mA 21, 28,
44
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device
bank; Active-Precharge;
t
RC =
t
RAS (MAX);
t
CK =
t
CK (MIN); DQ,
DM, and DQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle.
IDD3N 200 200 180 mA 20
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One
device bank active; Address and control inputs changing once per
clock cycle;
t
CK =
t
CK (MIN); IOUT = 0mA.
I
DD4R 660 660 580 mA 20, 42
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
device bank active; Address and control inputs changing once per
clock cycle;
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing
twice per clock cycle.
I
DD4W 780 640 540 mA 20
AUTO REFRESH CURRENT
t
REFC =
t
RFC (MIN)
I
DD5 1,160 1,160 1,120 mA 44
t
REFC = 7.8125µs
IDD5A 40 40 40 mA 24, 44
SELF REFRESH CURRENT: CKE
≤
0.2V
IDD6 20 20 20 mA 9
OPERATING CURRENT: Four device bank interleaving READs (BL =
4) with auto precharge,
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); Address
and control inputs change only during Active, READ, or WRITE
commands.
I
DD7 1,620 1,600 1,400 mA 20, 43
