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MT4VDDT864AG-26AB1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
64MB, 128MB, 256MB (x64, SR)
184-PIN DDR SDRAM UDIMM
pdf: 09005aef8085081a, source: 09005aef806e129d Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD4C8_16_32x64AG.fm - Rev. B 9/04 EN
10 ©2004 Micron Technology, Inc.
TER command to the mode register (with BA0 = 1 and
BA1 = 0) and will retain the stored information until it
is programmed again or the device loses power. The
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode regis-
ter (BA0/BA1 both low) to reset the DLL.
The extended mode register must be loaded when
all device banks are idle and no bursts are in progress,
and the controller must wait the specified time before
initiating any subsequent operation. Violating either
of these requirements could result in unspecified oper-
ation.
Output Drive Strength
The normal full drive strength for all outputs is
specified to be SSTL2, Class II. The x16 supports an
option for reduced drive. This option is intended for
the support of the lighter load and/or point-to-point
environments. The selection of the reduced drive
strength will alter the DQs and DQSs from SSTL2,
Class II drive strength to a reduced drive strength,
which is approximately 54 percent of the SSTL2, Class
II drive strength.
For detailed information on programmable and
reduced drive strength option, refer to the 128Mb,
256Mb, or 512Mb DDR SDRAM component data
sheets.
DLL Enable/Disable
The DLL must be enabled for normal operation.
DLL enable is required during power-up initialization
and upon returning to normal operation after having
disabled the DLL for the purpose of debug or evalua-
tion. (When the device exits self refresh mode, the DLL
is enabled automatically.) Any time the DLL is
enabled, 200 clock cycles must occur before a READ
command can be issued.
Figure 5: Extended Mode Register
Definition Diagram
NOTE:
1. BA1 and BA0 (E13 and E12 for 64MB, E14 and E13 for
128MB or 256MB) must be “0, 1” to select the Extended
Mode Register (vs. the base Mode Register).
2. The QFC# option is not supported.
Operating Mode
Normal Operation
All other states reserved
0
–
0
–
Valid
–
0
1
DLL
Enable
Disable
DLL
1
1
0
1
A9
A7
A6 A5 A4
A3
A8
A2
A1
A0
Extended Mode
Register (Ex)
Address Bus
9
7
654
3
8
2
1
0
E0
0
1
Drive Strength
Normal
Reduced
E1
E0
E1,
Operating Mode
A10
A11
BA1
BA0
10
11
12
13
E3E4
0
–
0
–
0
–
0
–
0
–
E6
E5
E7E8E9
0
–
0
–
E10E11
DS
DLL
1
1
0
1
A9
A7
A6 A5 A4
A3
A8
A2
A1
A0
Extended Mode
Register (Ex)
Address Bus
9
7
654
3
8
2
1
0
Operating Mode
A10
A11A12
BA1
BA0
10
11
12
1314
DS
64MB Module
128MB, 256MB Modules
0
–
E2
2
64MB, 128MB, 256MB (x64, SR)
184-PIN DDR SDRAM UDIMM
pdf: 09005aef8085081a, source: 09005aef806e129d Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD4C8_16_32x64AG.fm - Rev. B 9/04 EN
11 ©2004 Micron Technology, Inc.
Commands
Table 8, Commands Truth Table, and Table 9, DM
Operation Truth Table, provide a general reference of
available commands. For a more detailed description
of commands and operations, refer to the 128Mb,
256Mb, or 512Mb DDR SDRAM component data sheet.
NOTE:
1. DESELECT and NOP are functionally interchangeable.
2. BA0–BA1 provide device bank address and A0–A11 (64MB) or A0–A12 (128MB
, 256MB) provide row address.
3. BA0–BA1 provide device bank address; A0–A9 (64MB, 128MB) or A0–A9, A11 (256MB) provide column address; A10
HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.
4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ
bursts with auto precharge enabled and for WRITE bursts.
5. A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0–
BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0
= 1, BA1 = 0 select extended mode register; other combinations of BA0–BA1 are reserved). A0–A11 (64MB) or A0–A12
(128MB
, 256MB) provide the op-code to be written to the selected mode register.
Table 8: Commands Truth Table
CKE is HIGH for all commands shown except SELF REFRESH; all states and sequences not shown are illegal or reserved
NAME (FUNCTION) CS# RAS# CAS# WE# ADDR NOTES
DESELECT (NOP)
HXXX X 1
NO OPERATION (NOP)
LHHH X 1
ACTIVE (Select bank and activate row)
L L H H Bank/Row 2
READ (Select bank and column, and start READ burst)
LHLHBank/Col 3
WRITE (Select bank and column, and start WRITE burst)
L H L L Bank/Col 3
BURST TERMINATE
LHHL X 4
PRECHARGE (Deactivate row in bank or banks)
L L H L Code 5
AUTO REFRESH or SELF REFRESH (Enter self refresh mode)
LLLH X 6, 7
LOAD MODE REGISTER
LLLLOp-Code 8
Table 9: DM Operation Truth Table
Used to mask write data; provided coincident with the corresponding data
NAME (FUNCTION) DM DQS
WRITE Enable
L Valid
WRITE Inhibit
HX
64MB, 128MB, 256MB (x64, SR)
184-PIN DDR SDRAM UDIMM
pdf: 09005aef8085081a, source: 09005aef806e129d Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD4C8_16_32x64AG.fm - Rev. B 9/04 EN
12 ©2004 Micron Technology, Inc.
Absolute Maximum Ratings
Stresses greater than those listed may cause perma-
nent damage to the device. This is a stress rating only,
and functional operation of the device at these or any
other conditions above those indicated in the opera-
tional sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
V
DD Supply Voltage Relative to Vss . . . .-1V to +3.6V
V
DDQ Supply Voltage Rel. to Vss . . . . . . .-1V to +3.6V
V
REF and Inputs Voltage
Relative to V
SS . . . . . . . . . . . . . . . . . . . .-1V to +3.6V
I/O Pins Voltage
Relative to Vss. . . . . . . . . . . . . -0.5V to V
DDQ +0.5V
Operating Temperature,
T
A
(ambient - commercial) . . . . . . . . .0°C to +70°C
T
A
(ambient - industrial) . . . . . . . . .-40°C to +85°C
Storage Temperature (plastic) . . . . . .-55°C to +150°C
Short Circuit Output Current. . . . . . . . . . . . . . . .50mA
Table 10: DC Electrical Characteristics and Operating Conditions
Notes: 1–5, 14, 48; notes appear on pages 18–21; 0°C ≤ T
A
≤ +70°C
PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES
Supply Voltage
V
DD 2.3 2.7 V 32, 37
I/O Supply Voltage
V
DDQ 2.3 2.7 V 32, 37, 40
I/O Reference Voltage
V
REF 0.49 x VDDQ0.51 x VDDQ V 6, 40
I/O Termination Voltage (system)
V
TT VREF - 0.04 VREF + 0.04 V 7, 40
Input High (Logic 1) Voltage
V
IH(DC)VREF + 0.15 VDD + 0.3 V 25
Input Low (Logic 0) Voltage
V
IL(DC)-0.3VREF - 0.15 V 25
INPUT LEAKAGE CURRENT
Any input, 0V ≤ V
IN ≤ VDD,
V
REF pin 0V ≤ VIN ≤ 1.35V
(All other pins not under test = 0V)
Command/
Address, S#, CKE
I
I -8 8 µA 47
CK, CK#
II -4 4 µA 47
DM
I
I -2 2 µA 47
OUTPUT LEAKAGE CURRENT
(DQ pins are disabled; 0V ≤ VOUT ≤ VDDQ)
DQ, DQS
I
OZ -5 5 µA 47
OUTPUT LEVELS: Full drive option
High Current (V
OUT
= V
DD
Q - 0.373V, minimum V
REF
, minimum V
TT
)
IOH -16.8 – mA
33, 35
Low Current (V
OUT = 0.373V, maximum VREF, maximum VTT)
I
OL 16.8 – mA
OUTPUT LEVELS: Reduced drive option
High Current (V
OUT
= V
DD
Q - 0.763V, minimum V
REF
, minimum V
TT
)
IOHR -9 – mA
34, 35
Low Current (V
OUT = 0.763V, maximum VREF,maximum VTT)
I
OLR 9–mA
Table 11: AC Input Operating Conditions
Notes: 1–5, 14, 49; notes appear on pages 18–21; 0°C ≤ T
A
≤ +70°C; VDD = VDDQ = +2.5V ±0.2V
PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES
Input High (Logic 1) Voltage
V
IH(AC) VREF + 0.310 – V 12, 25, 36
Input Low (Logic 0) Voltage
V
IL(AC) – VREF - 0.310 V 12, 25, 36
I/O Reference Voltage
V
REF(AC) 0.49 x VDDQ 0.51 x VDDQV 6
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

MT4VDDT864AG-26AB1

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Manufacturer:
Micron
Description:
MODULE DDR SDRAM 64MB 184UDIMM
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