64MB, 128MB, 256MB (x64, SR)
184-PIN DDR SDRAM UDIMM
pdf: 09005aef8085081a, source: 09005aef806e129d Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD4C8_16_32x64AG.fm - Rev. B 9/04 EN
22 ©2004 Micron Technology, Inc.
Initialization
To ensure device operation the DRAM must be ini-
tialized as described below:
1. Simultaneously apply power to V
DD and VDDQ.
2. Apply V
REF and then VTT power.
3. Assert and hold CKE at a LVCMOS logic low.
4. Provide stable CLOCK signals.
5. Wait at least 200µs.
6. Bring CKE high and provide at least one NOP or
DESELECT command. At this point the CKE input
changes from a LVCMOS input to a SSTL2 input
only and will remain a SSTL_2 input unless a
power cycle occurs.
7. Perform a PRECHARGE ALL command.
8. Wait at least
t
RP time, during this time NOPs or
DESELECT commands must be given.
9. Using the LMR command program the Extended
Mode Register (E0 = 0 to enable the DLL and E1 =
0 for normal drive or E1 = 1 for reduced drive, E2
through En must be set to 0; where n = most sig-
nificant bit).
10. Wait at least
t
MRD time, only NOPs or DESELECT
commands are allowed.
11. Using the LMR command program the Mode Reg-
ister to set operating parameters and to reset the
DLL. Note at least 200 clock cycles are required
between a DLL reset and any READ command.
12. Wait at least
t
MRD time, only NOPs or DESELECT
commands are allowed.
13. Issue a PRECHARGE ALL command.
14. Wait at least
t
RP time, only NOPs or DESELECT
commands are allowed.
15. Issue an AUTO REFRESH command (Note this
may be moved prior to step 13).
16. Wait at least
t
RFC time, only NOPs or DESELECT
commands are allowed.
17. Issue an AUTO REFRESH command (Note this
may be moved prior to step 13).
18. Wait at least
t
RFC time, only NOPs or DESELECT
commands are allowed.
19. Although not required by the Micron device,
JEDEC requires a LMR command to clear the DLL
bit (set M8 = 0). If a LMR command is issued the
same operating parameters should be utilized as
in step 11.
20. Wait at least
t
MRD time, only NOPs or DESELECT
commands are allowed.
21. At this point the DRAM is ready for any valid com-
mand. Note 200 clock cycles are required between
step 11 (DLL Reset) and any READ command.
Figure 11: Initialization Flow Diagram
VDD and VDDQ Ramp
Apply VREF and VTT
CKE must be LVCMOS Low
Apply stable CLOCKs
Bring CKE High with a NOP command
Wait at least 200us
PRECHARGE ALL
Assert NOP or DESELECT for
t
RP time
Configure Extended Mode Register
Configure Load Mode Register and reset DLL
Assert NOP or DESELECT for
t
MRD time
Assert NOP or DESELECT for
t
MRD time
PRECHARGE ALL
Issue AUTO REFRESH command
Assert NOP or DESELECT for
t
RFC time
Optional LMR command to clear DLL bit
Assert NOP or DESELECT for
t
MRD time
DRAM is ready for any valid command
Step
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Assert NOP or DESELECT commands for
t
RFC
Issue AUTO REFRESH command
Assert NOP or DESELECT for
t
RP time
