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MT4VDDT864AG-26AB1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
64MB, 128MB, 256MB (x64, SR)
184-PIN DDR SDRAM UDIMM
pdf: 09005aef8085081a, source: 09005aef806e129d Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD4C8_16_32x64AG.fm - Rev. B 9/04 EN
19 ©2004 Micron Technology, Inc.
140.6µs (64MB) or 70.3µs (128MB, 256MB); burst
refreshing or posting by the DRAM controller
greater than eight refresh cycles is not allowed.
22. The valid data window is derived by achieving
other specifications:
t
HP (
t
CK/2),
t
DQSQ, and
t
QH
(
t
QH =
t
HP -
t
QHS). The data valid window derates
directly porportional with the clock duty cycle
and a practical data valid window can be derived.
The clock is allowed a maximum duty cycle varia-
tion of 45/55, beyond which functionality is
uncertain. Figure 6, Derating Data Valid Window
(t
QH =
t
HP -
t
QHS), shows derating curves for duty
cycles ranging between 50/50 and 45/55.
23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not
result in a fail value. CKE is HIGH during
REFRESH command period (
t
RFC [MIN]) else
CKE is LOW (i.e., during standby).
25. To maintain a valid level, the transitioning edge of
the input must:
a. Sustain a constant slew rate from the current
AC level through to the target AC level, V
IL (AC)
or V
IH (AC).
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to
maintain at least the target DC level, V
IL (DC)
or V
IH (DC).
26. JEDEC specifies CK and CK# input slew rate must
be ≥
1V/ns (2V/ns differentially).
27. DQ and DM input slew rates must not deviate
from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps must be added to
t
DS and
t
DH for each 100mv/ns reduction in slew rate. If
slew rate exceeds 4V/ns, functionality is uncer-
tain.
28. V
DD must not vary more than 4 percent if CKE is
not active while any bank is active.
29. The clock is allowed up to ±150ps of jitter. Each
timing parameter is allowed to vary by the same
amount.
30.
t
HP min is the lesser of
t
CL minimum and
t
CH
minimum actually applied to the device CK and
CK# inputs, collectively during bank active.
31. READs and WRITEs with auto precharge are not
allowed to be issued until
t
RAS (MIN) can be satis-
fied prior to the internal precharge command
being issued.
Figure 6: Derating Data Valid Window
(t
QH =
t
HP -
t
QHS)
3.750
3.700
3.650
3.600
3.550
3.500
3.450
3.400
3.350
3.300
3.250
2.500
2.463
2.425
2.388
2.350
2.313
2.275
2.238
2.200
2.163
2.125
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 47/53 46.5/54.5 46/54 45.5/55.5 45/55
Clock Dut
y
C
y
cle
ns
-335
-262/-26A/-265 @
t
CK = 10ns
-262/-26A/-265 @
t
CK = 7.5ns
NA
64MB, 128MB, 256MB (x64, SR)
184-PIN DDR SDRAM UDIMM
pdf: 09005aef8085081a, source: 09005aef806e129d Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD4C8_16_32x64AG.fm - Rev. B 9/04 EN
20 ©2004 Micron Technology, Inc.
32. Any positive glitch in the nominal voltage must be
less than 1/3 of the clock and not more than
+400mV or 2.9V, whichever is less. Any negative
glitch must be less than 1/3 of the clock cycle and
not exceed either 300mV or 2.2V, whichever is
more positive. However, the DC average cannot be
below 2.3V minimum.
33. Normal Output Drive Curves:
a. The full variation in driver pull-down current
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 7,
Normal Drive Pull-Down Characteristics.
b. The variation in driver pull-down current
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 7, Normal Drive Pull-Down
Characteristics.
c. The full variation in driver pull-up current
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 8,
Normal Drive Pull-Up Characteristics.
d. The variation in driver pull-up current within
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of Figure
8, Normal Drive Pull-Up Characteristics.
e. The full variation in the ratio of the maximum
to minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0 Volt,
and at the same voltage and temperature.
f. The full variation in the ratio of the nominal
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0V.
34. Reduced Output Drive Curves:
a)
The full variation in driver pull-down current from
minimum to maximum process, temperature and
voltage will lie within the outer bounding lines of
the V-I curve of Figure 9, Reduced Drive Pull-
Down Characteristics, on page 21.
b)The variation in driver pull-down current within
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of Figure 9,
Reduced Drive Pull-Down Characteristics, on
page 21.
c)The full variation in driver pull-up current from
minimum to maximum process, temperature and
voltage will lie within the outer bounding lines of
the V-I curve of Figure10, Reduced Drive Pull-Up
Characteristics, on page 21.
d)The variation in driver pull-up current within
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of
Figure 10, Reduced Drive Pull-Up Characteristics,
on page21
.
e)The full variation in the ratio of the maximum to
minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage.
Figure 7: Normal Drive Pull-Down
Characteristics
Figure 8: Normal Drive Pull-Up
Characteristics
160
140
IOUT (mA)
VOUT (V)
Nominal low
Minimum
Nominal high
Maximum
120
100
80
60
40
20
0
0.0 0.5 1.0 1.5 2.0 2.5
VOUT (V)
0
-20
IOUT (mA)
Nom
inal low
Minimum
Nominal high
Maximum
-40
-60
-80
-100
-120
-140
-160
-180
-200
0.0 0.5 1.0 1.5 2.0 2.5
VDDQ - VOUT (V)
64MB, 128MB, 256MB (x64, SR)
184-PIN DDR SDRAM UDIMM
pdf: 09005aef8085081a, source: 09005aef806e129d Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD4C8_16_32x64AG.fm - Rev. B 9/04 EN
21 ©2004 Micron Technology, Inc.
Figure 9: Reduced Drive Pull-Down
Characteristics
Figure 10: Reduced Drive Pull-Up
Characteristics
f)The full variation in the ratio of the nominal
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source voltages
from 0.1V to 1.0V.
g. The voltage levels used are derived from a mini-
mum V
DD level and the referenced test load. In
practice, the voltage levels obtained from a
properly terminated bus will provide signifi-
cantly different voltage values.
35. V
IH overshoot: VIH (MAX) = VDDQ + 1.5V for a
pulse width ≤ 3ns and the pulse width can not be
greater than 1/3 of the cycle rate. VIL undershoot:
V
IL (MIN) = -1.5V for a pulse width ≤ 3ns and the
pulse width can not be greater than 1/3 of the
cycle rate.
36. V
DD and VDDQ must track each other.
37.
t
HZ (MAX) takes precedence over
t
DQSCK (MAX)
+
t
RPST (MAX) condition.
t
LZ (MIN) will prevail
over
t
DQSCK (MIN) +
t
RPRE (MAX) condition.
38.
t
RPST end point and
t
RPRE begin point are not
referenced to a specific voltage level but specify
when the device output is no longer driving
(
t
RPST), or begins driving (
t
RPRE).
39. During initialization, V
DDQ, VTT, and VREF must
be equal to or less than V
DD + 0.3V. Alternatively,
V
TT may be 1.35V maximum during power up,
even if V
DD/VDDQ are 0V, provided a minimum of
42Ω of series resistance is used between the V
TT
supply and the input pin.
40. For -335, -262, -26A and -265 speed grades, I
DD3N
is specified to be 35mA per DDR SDRAM at 100
MHz.
41. The current Micron part operates below the slow-
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
42. Random addressing changing and 50 percent of
data changing at every transfer.
43. Random addressing changing and 100 percent of
data changing at every transfer.
44. CKE must be active (high) during the entire time a
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
t
REF later.
45. I
DD2N specifies the DQ, DQS, and DM to be driven
to a valid high or low logic level. I
DD2Q is similar
to I
DD2F except IDD2Q specifies the address and
control inputs to remain stable. Although IDD2F,
I
DD2N, and IDD2Q are similar, IDD2F is “worst
case.”
46. Whenever the operating frequency is altered, not
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles.
47. Leakage number reflects the worst case leakage
possible through the module pin, not what each
memory device contributes.
48. When an input signal is HIGH or LOW, it is
defined as a steady state logic HIGH or LOW.
49. The -335 speed grade will operate with
t
RAS (MIN)
= 40ns and
t
RAS (MAX) = 120,000ns at any slower
frequency.
0
10
20
30
40
50
60
70
80
0.0 0.5 1.0 1.5 2.0 2.5
V
OUT
(V)
I
OUT
(mA)
Nominal low
Minimum
Nominal high
Maximum
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0 0.5 1.0 1.5 2.0 2.5
V
DD
Q - V
OUT
(V)
I
OUT
(mA)
Minimum
Maximum
Nominal low
Nominal high
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MT4VDDT864AG-26AB1

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Manufacturer:
Micron
Description:
MODULE DDR SDRAM 64MB 184UDIMM
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