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MT4VDDT864AG-26AB1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
64MB, 128MB, 256MB (x64, SR)
184-PIN DDR SDRAM UDIMM
pdf: 09005aef8085081a, source: 09005aef806e129d Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD4C8_16_32x64AG.fm - Rev. B 9/04 EN
25 ©2004 Micron Technology, Inc.
NOTE:
1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising
edge of SDA.
2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
t
WRC) is the time from a valid stop condition of a write sequence to the end of
the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
Table 19: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to Vss; VDDSPD = +2.3V to +3.6V
PARAMETER/CONDITION SYMBOL MIN MAX UNITS
SUPPLY VOLTAGE
V
DD 2.3 3.6 V
INPUT HIGH VOLTAGE: Logic 1; All inputs
V
IH VDD x 0.7 VDD + 0.5 V
INPUT LOW VOLTAGE: Logic 0; All inputs
V
IL -1 VDD x 0.3 V
OUTPUT LOW VOLTAGE: IOUT = 3mA
V
OL –0.4V
INPUT LEAKAGE CURRENT: V
IN = GND to VDD
ILI –10µA
OUTPUT LEAKAGE CURRENT: V
OUT = GND to VDD
ILO –10µA
STANDBY CURRENT: SCL = SDA = V
DD
- 0.3V; All other inputs = V
SS
or V
DD
ISB –30µA
POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz
I
DD –2mA
Table 20: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES
SCL LOW to SDA data-out valid
t
AA 0.2 0.9 µs 1
Time the bus must be free before a new transition can start
t
BUF 1.3 µs
Data-out hold time
t
DH 200 ns
SDA and SCL fall time
t
F 300 ns 2
Data-in hold time
t
HD:DAT 0 µs
Start condition hold time
t
HD:STA 0.6 µs
Clock HIGH period
t
HIGH 0.6 µs
Noise suppression time constant at SCL, SDA inputs
t
I50ns
Clock LOW period
t
LOW 1.3 µs
SDA and SCL rise time
t
R0.3µs2
SCL clock frequency
f
SCL 400 KHz
Data-in setup time
t
SU:DAT 100 ns
Start condition setup time
t
SU:STA 0.6 µs 3
Stop condition setup time
t
SU:STO 0.6 µs
WRITE cycle time
t
WRC 10 ms 4
64MB, 128MB, 256MB (x64, SR)
184-PIN DDR SDRAM UDIMM
pdf: 09005aef8085081a, source: 09005aef806e129d Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD4C8_16_32x64AG.fm - Rev. B 9/04 EN
26 ©2004 Micron Technology, Inc.
Table 21: Serial Presence- Detect Matrix
“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 27
BYTE DESCRIPTION ENTRY (VERSION)
MT4VDDT864A MT4VDDT1664A MT4VDDT3264A
0
Number of SPD Bytes Used by Micron
128 80 80 80
1
Total Number of Bytes in SPD Device
256 08 08 08
2
Fundamental Memory Type
SDRAM DDR 07 07 07
3
Number of Row Addresses on Assembly
12 or 13 0C 0D 0D
4
Number of Column Addresses on
Assembly
9 or 10 09 09 0A
5
Number of Physical Ranks on DIMM
1010101
6
Module Data Width
64 40 40 40
7
Module Data Width (Continued)
0000000
8
Module Voltage Interface Levels
SSTL 2.5V 04 04 04
9
SDRAM Cycle Time,
t
CK, (CAS Latency
= 2.5) (See note 1)
6ns (-335)
7ns (-262/-26A)
7.5ns (-265)
60
70
75
60
70
75
60
70
75
10
SDRAM Access From Clock,
t
AC, (CAS
Latency = 2.5) (See note 1)
0.70ns (-335)
0.75ns (-262/-26A/-265)
70
75
70
75
70
75
11
Module Configuration Type
Non-ECC 00 00 00
12
Refresh Rate/Type
15.6µs or 7.8µs/SELF 80 82 82
13
DDR SDRAM Device Width
x16 10 10 10
14
Error-checking SDRAM Data Width
None 00 00 00
15
Minimum Clock Delay, Back-to-Back
Random Column Access
1 clock 01 01 01
16
Burst Lengths Supported
2, 4, 8 0E 0E 0E
17
Number of Banks on SDRAM Device
4040404
18
CAS Latencies Supported
2, 2.5 0C 0C 0C
19
CS Latency
0010101
20
WE Latency
1020202
21
SDRAM Module Attributes
Unbuffered, Diff CLK 20 20 20
22
SDRAM Device Attributes: General
Fast/Concurrent AP C1 C1 C1
23
SDRAM Cycle Time,
t
CK (CAS Latency =
2) (See note 1)
7.5ns (-335/-262/-26A)
10ns (-265)
75
A0
75
A0
75
A0
24
SDRAM Access From CK,
t
AC (CAS
Latency = 2) (See note 1)
0.70ns (-335)
0.75ns (-262/-26A/-265)
70
75
70
75
70
75
25
SDRAM Cycle Time,
t
CK, (CAS Latency
= 1.5)
N/A 00 00 00
26
SDRAM Access from CK,
t
AC, (CAS
Latency = 1.5)
N/A 00 00 00
27
Minimum Row Precharge Time,
t
RP
(see note 4)
18ns (-335)
15ns (-262)
20ns (-26A/-265)
48
3C
50
48
3C
50
48
3C
50
28
Minimum Row Active to Row Active,
t
RRD
12ns (-335)
15ns (-262/-26A/-265)
30
3C
30
3C
30
3C
29
Minimum RAS# to CAS# Delay,
t
RCD
(see note 4)
18ns (-335)
15ns (-262)
20ns (-26A/-265)
48
3C
50
48
3C
50
48
3C
50
30
Minimum RAS# Pulse Width,
t
RAS
(See note 2)
42ns (-335)
45ns (-262/-26A/-265)
2A
2D
2A
2D
2A
2D
64MB, 128MB, 256MB (x64, SR)
184-PIN DDR SDRAM UDIMM
pdf: 09005aef8085081a, source: 09005aef806e129d Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD4C8_16_32x64AG.fm - Rev. B 9/04 EN
27 ©2004 Micron Technology, Inc.
NOTE:
1. Value for -26A/-265
t
CK set to 7ns (0x70) for optimum BIOS compatibility. Actual device spec value is 7.5ns.
2. The value of
t
RAS used for the -26A/-265 module is calculated from
t
RC-
t
RP. Actual device spec. value is 40ns.
3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is
represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster mini-
mum slew rate is met.
4. The value of
t
RP,
t
RCD and
t
RAP for -335 modules indicated as 18ns to align with industry specifications; actual DDR
SDRAM device specification is 15ns.
31
Module Rank Density
64MB, 128MB, or
256MB
10 20 40
32
Address and Command Setup Time,
t
IS
(See note 3)
0 .8ns (-335)
1.0ns (-262/-26A/-265)
80
A0
80
A0
80
A0
33
Address and Command Hold Time,
t
IH
(See note 3)
0.8ns (-335)
1.0ns (-262/-26A/-265)
80
A0
80
A0
80
A0
34
Data/Data Mask Input Setup Time,
t
DS
0.45ns (-335)
0.5ns (-262/-26A/-265)
45
50
45
50
45
50
35
Data/Data Mask Input Hold Time,
t
DH
0.45ns (-335)
0.5ns (-262/-26A/-265)
45
50
45
50
45
50
36-40
Reserved
00 00 00
41
Minimum Active/Auto Refresh Time,
t
RC
60ns (-335/-262)
65ns (-26A/-265)
3C
41
3C
41
3C
41
42
Minimum Auto Refresh to Active/
Auto Refresh Command Period,
t
RFC
72ns (-335)
75ns (-262/-26A/-265)
48
4B
48
4B
48
4B
43
Maximum Cycle Time,
t
CK (MAX)
12ns (-335)
13ns (-262/-26A/-265)
30
34
30
34
30
34
44
Maximum DQS-DQ Skew Time,
t
DQSQ
0.45ns (-335)
0.5ns (-262/-26A/-265)
2D
32
2D
32
2D
32
45
Maximum Read Data Hold Skew
Factor,
t
QHS
0.55ns (-335)
0.75ns (-262/-26A/-265)
55
75
55
75
55
75
46
Reserved
00 00 00
47
DIMM Height
Standard 01 01 01
48–61
Reserved
00 00 00
62
SPD Revision
Release 1.0 10 10 10
63
Checksum For Bytes 0-62
-335
-262
-26A
-265
FC
8F
BC
EC
0F
A2
CF
FF
33
C3
F0
20
64
Manufacturer’s JEDEC ID Code
MICRON 2C 2C 2C
65-71
Manufacturer’s JEDEC ID Code (cont.)
FF FF FF
72
Manufacturing Location
1 - 12 01 - 0C 01 - 0C 01 - 0C
73-90
Module Part Number (ASCII)
Variable Data Variable Data Variable Data
91
PCB Identification Code
1 - 9 01 - 09 01 - 09 01 - 09
92
Identification Code (Continued)
0000000
93
Year of Manufacture in BCD
Variable Data Variable Data Variable Data
94
Week of Manufacture in BCD
Variable Data Variable Data Variable Data
95-98
Module Serial Number
Variable Data Variable Data Variable Data
99-127
Manufacturer-Specific Data (RSVD)
–––
Table 21: Serial Presence- Detect Matrix (Continued)
“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 27
BYTE DESCRIPTION ENTRY (VERSION)
MT4VDDT864A MT4VDDT1664A MT4VDDT3264A
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

MT4VDDT864AG-26AB1

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Manufacturer:
Micron
Description:
MODULE DDR SDRAM 64MB 184UDIMM
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