EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
XRD98L23
8-Bit, High-speed Linear CIS/CCD Sensor
Signal Processor with Serial Control
November 2002-2
FEATURES
· 8-Bit Resolution, No Missing Codes
· One-channel 10MSPS Pixel Rate
· Dual-channel 5MSPS Pixel Rate
· Three-channel 3 MSPS Pixel Rate
· 6-bit Programmable Gain Amplifier
· 8-bit Programmable Offset Adjustment
· CIS or CCD Compatibility
· Internal Clamp for CIS or CCD AC Coupled
Configurations
· 3.3V Operation & I/O Compatibility
· Serial Load Control Registers
· Low Power CMOS: 75mW-typ
· Low Cost 20-Lead Packages
· USB Compliant
APPLICATIONS
· Check Scanners
· General Purpose CIS or CCD Imaging
· Low Cost Data Acquisition
· Simple and Direct Interface to Canon 600 DPI
Sensors
ORDERING INFORMATION
Package Type Temperature Range Part Number
20-Lead SOIC 0°C to +70°C XRD98L23ACD
20-Lead SSOP 0°C to +70°C XRD98L23ACU
GENERAL DESCRIPTION
The XRD98L23 is a complete linear CIS or CCD sensor
signal processor on a single monolithic chip. The
XRD98L23 includes a high speed 8-bit resolution ADC,
a 6-bit Programmable Gain Amplifier with gain adjust-
ment of 1 to 10, and a typical 8-bit programmable input
referred offset calibration range of 480mV.
In the CCD configuration the input signal is AC coupled
with an external capacitor. An internal clamp sets the
black level. In the CIS configuration, the clamp switch
can be disabled and the CIS output signal is DC
coupled from the CIS sensor to the XRD98L23. The
CIS signal is level shifted to VRB in order to use the full
range of the ADC. In the CIS configuration the input can
also be AC coupled similar to the CCD configuration.
This enables CIS signals with large black levels to be
internally clamped to a DC reference equal to the black
level. The DC reference is internally subtracted from
the input signal.
The CIS configuration can also be used in other
applications that do not require CDS function, such as
low cost data acquisition.
Rev. 1.00
XRD98L23
2
Rev. 1.00
Figure 1. Functional Block Diagram
RED
GRN
BLU
VDCEXT
VREF+
DB7:0
DVDD
DGND
AVDD
AGND
ADCCLK
CLAMP
SYNCH
PGA
TIMING
&
CONTROL LOGIC
AVDD
6-BIT GAIN
REGISTERS
8-BIT
ADC
RL
AGND
DATA
I/O
PORT
BUFFER
VRT
VRB
Triple
S/H
&
3-1
MUX
8-BIT DAC
8
8
8-BIT OFFSET
REGISTERS
6
8
+
_
AGND
V
DCREF
DC/AC
INT/EXT_V
DCREF
CIS/CCD
G<5:0>
O<7:0>
R G B
R G B
CLP
CLAMP
Power
Down
Power
Down
VRT
CCD
CIS
VBG
CIS REF Circuit
CIS REF Circuit
DC Reference
XRD98L23
3
Rev. 1.00
1
2
3
4
5
6
7
8
9
10
AVDD
VREF+
XRD98L23ACD
20
19
18
17
16
15
14
13
12
RED
GRN
BLU
VDCEXT
AGND
DVDD
DB0
DB1
DB2
DB4
DGND ADCCLK
DB3
11
DB5/SCLK
DB6/SDATA
DB7/LD
CLAMP
SYNCH
20-Lead SOIC
PIN DESCRIPTION
Pin # Symbol Description
1 DVDD Digital VDD (for Output Drivers)
2 DB0 Data Output Bit 0
3 DB1 Data Output Bit 1
4 DB2 Data Output Bit 2
5 DB3 Data Output Bit 3
6 DB4 Data Output Bit 4
7 DB5/SCLK Data Output Bit 5 & Data Input SCLK
8 DB6/SDATA Data Output Bit 6 & Data Input SDATA
9 DB7/LD Data Output Bit 7 & LD
10 DGND Digital Ground (for Output Drivers)
11 ADCCLK A/D Converter Clock
12 CLAMP Clamp and Video Sample Clock
13 SYNCH Start of New Line and Serial Data Input Control
14 AGND Analog Ground
15 VREF+ A/D Positive Reference for Decoupling Cap
16 VDCEXT External DC Reference
17 BLU Blue Input
18 GRN Green Input
19 RED Red Input
20 AVDD Analog Power Supply
PIN CONFIGURATION

XRD98L23ACU

Mfr. #:
Manufacturer:
MaxLinear
Description:
Analog Front End - AFE
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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