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XRD98L23ACU

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
XRD98L23
22
Rev. 1.00
RL
VRT
VRB
VDD
RED/GRN/BLU
XRD98L23
CLAMP
C
C
D
M
U
X
N/C
Figure 16. CCD AC Coupled Application
XRD98L23
23
Rev. 1.00
AVDD
VCC (5V - 15V)
DGND
AGND
DIGITAL
ASIC
C
C
D
N/C
100PF
100PF
100PF
XRD98L23
DVDD
1
DB0
2
DB1
3
DB2
4
DB3
5
DB4
6
DB5/SCLK
7
DB6/SDATA
8
DB7/LD
9
DGND
10
ADCCLK
11
CLAM
P
12
SYNCH
13
AGND
14
VREF+
15
VDCEXT
16
BLU
17
GRN
18
RED
19
AVDD
20
DVDD (3V)
Figure 17. Typical Application Circuitry Triple Channel CCD
AC Coupled Inverted Mode
XRD98L23
24
Rev. 1.00
(CLAMP Enabled)
BLU
GRN
RED
ADCCLK
CLAMP
DATA
PIXEL-BY-PIXEL 3 CHANNEL CCD -- AC Coupled
tdv
RED (N-6)
N+1 Pixel
CONVERT
RED (N)
CONVERT
GRN (N)
CONVERT
BLU (N)
TRACK
RED (N)
TRACK
GRN (N)
TRACK
RED (N+1)
TRACK
BLU (N)
CONVERT
RED (N+1)
tdv
tdv tdvtdv
N/A
GRN (N-6) N/A
BLU (N-6)
N/A
CLAMP
tsa
SYNCH
tsypw
tclp=10ns
tap
tclp=10ns
N+1 Pixel
N+1 Pixel
N Pixel
N Pixel
N Pixel
Simultaneous
Sample
trars
ADCCLK Events
3rd ↓ Simultaneous RED/GRN/BLU Sample Every 3rd CLK.
Convert RED, S/H GRN, S/H BLU.
All ↓ Data Out
↑ Non-valid Data Out
HI ADC Track PGA Output
LO ADC Hold/Convert
CLAMP Events
HI Internal Clamp Enabled
LO Internal RED/GRN/BLU Tracking Enabled
SYNCH Events
HI Reset Internal Mux to Red, Output Bus is Tri-stated
LO Increment Mux Color on Falling Edge of ADCCLK
Table 4.
Figure 18. Timing Diagram for Figure 17
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32

XRD98L23ACU

Mfr. #:
Buy XRD98L23ACU
Manufacturer:
MaxLinear
Description:
Analog Front End - AFE
Lifecycle:
New from this manufacturer.
Delivery:
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