REV. B
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AD73322
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2000
a
Low Cost, Low Power CMOS
General-Purpose Dual Analog Front End
FEATURES
Two 16-Bit A/D Converters
Two 16-Bit D/A Converters
Programmable Input/Output Sample Rates
78 dB ADC SNR
77 dB DAC SNR
64 kS/s Maximum Sample Rate
–90 dB Crosstalk
Low Group Delay (25 s Typ per ADC Channel,
50 s Typ per DAC Channel)
Programmable Input/Output Gain
Flexible Serial Port which Allows Up to Four Dual
Codecs to be Connected in Cascade Giving Eight
I/O Channels
Single (+2.7 V to +5.5 V) Supply Operation
73 mW Typ Power Consumption at 3.0 V
On-Chip Reference
28-Lead SOIC and 44-Lead LQFP Packages
APPLICATIONS
General Purpose Analog I/O
Speech Processing
Cordless and Personal Communications
Telephony
Active Control of Sound and Vibration
Data Communications
Wireless Local Loop
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The AD73322 is a dual front-end processor for general-purpose
applications including speech and telephony. It features two
16-bit A/D conversion channels and two 16-bit D/A conversion
channels. Each channel provides 77␣ dB signal-to-noise ratio
over a voiceband signal bandwidth. It also features an input-to-
output gain network in both the analog and digital domains.
This is featured on both codecs and can be used for impedance
matching or scaling when interfacing to Subscriber Line Inter-
face Circuits (SLICs).
The AD73322 is particularly suitable for a variety of applica-
tions in the speech and telephony area, including low bit rate,
high quality compression, speech enhancement, recognition, and
synthesis. The low group delay characteristic of the part makes
it suitable for single or multichannel active control applications.
The A/D and D/A conversion channels feature programmable
input/output gains with ranges of 38 dB and 21 dB respectively.
An on-chip reference voltage is included to allow single-supply
operation. This reference is programmable to accommodate
either 3 V or 5 V operation.
The sampling rate of the codecs is programmable with four
separate settings, offering 64 kHz, 32 kHz, 16 kHz and 8 kHz
sampling rates (from a master clock of 16.384 MHz).
A serial port (SPORT) allows easy interfacing of single or cas-
caded devices to industry standard DSP engines. The SPORT
transfer rate is programmable to allow interfacing to both fast
and slow DSP engines.
The AD73322 is available in 28-lead SOIC and 44-lead LQFP
packages.
REFCAP
SDOFS
ADC CHANNEL 1
REFERENCE
DAC CHANNEL 1
ADC CHANNEL 2
DAC CHANNEL 2
SPORT
AVDD1 AVDD2
DVDD
REFOUT
VFBP1
VINP1
VINN1
VFBN1
VOUTP1
VOUTN1
VFBP2
VINP2
VINN2
VFBN2
VOUTP2
VOUTN2
AGND1 AGND2 DGND
SDO
MCLK
RESET
SE
SCLK
SDIFS
SDI
AD73322
AD73322* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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DOCUMENTATION
Application Notes
AN-211: The Alexander Current-Feedback Audio Power
Amplifier
AN-327: DAC ICs: How Many Bits Is Enough?
Data Sheet
AD73322: Low Cost, Low Power CMOS General-Purpose
Dual Analog Front End Data Sheet
REFERENCE MATERIALS
Technical Articles
Benchmarking Integrated Audio: Why CPU Usage Alone
No Longer Predicts User Experience
DESIGN RESOURCES
AD73322 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
View all AD73322 EngineerZone Discussions.
SAMPLE AND BUY
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TECHNICAL SUPPORT
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number.
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–2–
REV. B
AD73322–SPECIFICATIONS
1
AD73322A
Parameter Min Typ Max Units Test Conditions/Comments
REFERENCE 5VEN = 0
REFCAP
Absolute Voltage, VREFCAP 1.08 1.2 1.32 V
REFCAP TC 50 ppm/°C 0.1 µF Capacitor Required from
REFOUT REFCAP to AGND2
Typical Output Impedance 130
Absolute Voltage, V
REFOUT
1.08 1.2 1.32 V Unloaded
Minimum Load Resistance 1 k
Maximum Load Capacitance 100 pF
INPUT AMPLIFIER
Offset ±1.0 mV
Maximum Output Swing 1.578 V Max Output Swing = (1.578/1.2) × VREFCAP
Feedback Resistance 50 f
C
= 32 kHz
Feedback Capacitance 100 pF
ANALOG GAIN TAP
Gain at Maximum Setting +1
Gain at Minimum Setting –1
Gain Resolution 5 Bits Gain Step Size = 0.0625
Gain Accuracy ±1.0 % Output Unloaded
Settling Time 1.0 µs Tap Gain Change of –FS to +FS
Delay 0.5 µs
ADC SPECIFICATIONS 5VEN = 0
Maximum Input Range at VIN
2, 3
1.578 V p-p Measured Differentially
–2.85 dBm Max Input = (1.578/1.2) × VREFCAP
Nominal Reference Level at VIN 1.0954 V p-p Measured Differentially
(0 dBm0) –6.02 dBm
Absolute Gain
PGA = 0 dB –0.5 0.4 +1.2 dB 1.0 kHz, 0 dBm0
PGA = 38 dB –1.5 –0.7 +0.1 dB 1.0 kHz, 0 dBm0
Gain Tracking Error ±0.1 dB 1.0 kHz, +3 dBm0 to –50 dBm0
Signal to (Noise + Distortion) Refer to Figure 5
PGA = 0 dB 72 78 dB 300 Hz to 3400 Hz; f
SAMP
= 64 kHz
78 dB 300 Hz to 3400 Hz; f
SAMP
= 8 kHz
55 57 dB 0 Hz to f
SAMP
/2; f
SAMP
= 64 kHz
PGA = 38 dB 52 56 dB 300 Hz to 3400 Hz; f
SAMP
= 64 kHz
Total Harmonic Distortion
PGA = 0 dB –84 –73 dB 300 Hz to 3400 Hz; f
SAMP
= 64 kHz
PGA = 38 dB –70 –60 dB 300 Hz to 3400 Hz; f
SAMP
= 64 kHz
Intermodulation Distortion –65 dB PGA = 0 dB
Idle Channel Noise –71 dBm0 PGA = 0 dB
Crosstalk ADC-to-DAC –100 dB ADC Input Signal Level: 1.0 kHz, 0 dBm0
DAC Input at Idle
ADC-to-ADC –100 dB ADC1 Input Signal Level: 1.0 kHz, 0 dBm0
ADC2 Input at Idle. Input Amplifiers Bypassed
–70 dB Input Amplifiers Included in Input Channel
DC Offset –30 +10 +45 mV PGA = 0 dB
Power Supply Rejection –65 dB Input Signal Level at AVDD and DVDD
Pins: 1.0 kHz, 100 mV p-p Sine Wave
Group Delay
4, 5
25 µs
Input Resistance at PGA
2, 4, 6
20 k Input Amplifiers Bypassed
DIGITAL GAIN TAP
Gain at Maximum Setting +1
Gain at Minimum Setting –1
Gain Resolution 16 Bits Tested to 5 MSBs of Settings
Delay 25 µs Includes DAC Delay
Settling Time 100 µs Tap Gain Change from –FS to +FS; Includes
DAC Settling Time
(AVDD = +3 V 10%; DVDD = +3 V 10%; DGND = AGND = 0 V, f
DMCLK
=
16.384 MHz, f
SAMP
= 64 kHz; T
A
= T
MIN
to T
MAX
, unless otherwise noted)

AD73322LARUZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog Front End - AFE Dual-Ch 3V Front-End Processor
Lifecycle:
New from this manufacturer.
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