AD73322
–35–REV. B
DSP SOFTWARE CONSIDERATIONS WHEN
INTERFACING TO THE AD73322
It is important when choosing the operating mode and hardware
configuration of the AD73322 to be aware of their implications
for DSP software operation. The user has the flexibility of
choosing from either FSLB or nonFSLB when deciding on DSP
to AFE connectivity. There is also a choice to be made between
using autobuffering of input and output samples or simply
choosing to accept them as individual interrupts. As most mod-
ern DSP engines support these modes, this appendix will at-
tempt to discuss these topics in a generic DSP sense.
Operating Mode
The AD73322 supports two basic operating modes: Frame Sync
Loop Back (FSLB) and nonFSLB (See Interfacing section). As
described previously, FSLB has some limitations when used in
Mixed Mode but is very suitable for use with the autobuffering
feature that is offered on many modern DSPs. Autobuffering
allows the user to specify the number of input or output words
(samples) that are transferred before a specific Tx or Rx SPORT
interrupt is generated. Given that the AD73322 outputs two
sample words per sample period, it is possible using autobuffer-
ing to have the DSP’s SPORT generate a single interrupt on
receipt of the second of the two sample words. Additionally,
both samples could be stored in a data buffer within the data
memory store. This technique has the advantage of reducing the
number of both Tx and Rx SPORT interrupts to a single one at
each sample interval. The user also knows where each sample is
stored. The alternative is to handle a larger number of SPORT
interrupts (twice as many in the case of a single AD73322) while
also having some status flags to indicate where each new sample
comes from (or is destined for).
Mixed-Mode Operation
To take full advantage of mixed-mode operation, it is necessary
to configure the DSP/Codec interface in nonFSLB and to dis-
able autobuffering. This allows a variable numbers of words to
be sent to the AD73322 in each sample period—the extra words
being control words which are typically used to update gain
settings in adaptive control applications. The recommended
sequence for updating control registers in mixed-mode is to
send the control word(s) first before the DAC update word.
It is possible to use mixed-mode operation when configured in
FSLB, but it is necessary to replace the DAC update with a
control word write in each sample period which may cause some
discontinuity in the output signal due to a sample point being
missed and the previous sample being repeated. This however
may be acceptable in some cases as the effect may be masked by
gain changes, etc.
Interrupts
The AD73322 transfers and receives information over the serial
connection from the DSP’s SPORT. This occurs following reset
—during the initialization phase—and in both data-mode and
mixed-mode. Each transfer of data to or from the DSP can
cause a SPORT interrupt to occur. However even in FSLB
configuration where serial transfers in and out of the DSP are
synchronous, it is important to note that Tx and Rx interrupts
do not occur at the same time due to the way that Tx and Rx
interrupts are generated internally within the DSP’s SPORT.
This is especially important in time critical control loop applica-
tions where it may be necessary to use Rx interrupts only, as the
relative positioning of the Tx interrupts relative to the Rx inter-
rupts in a single sample interval are not suitable for quick up-
date of new DAC positions.
Initialization
Following reset, the AD73322 is in its default condition which
ensures that the device is in Control Mode and must be pro-
grammed or initialized from the DSP to start conversions. As
communications between AD73322 and the DSP are interrupt
driven, it is usually not practical to embed the initialization
codes into the body of the initialization routine. It is more prac-
tical to put the sequence of initialization codes in a data (or
program) memory buffer and to access this buffer with a pointer
that is updated on each interrupt. If a circular buffer is used, it
allows the interrupt routine to check when the circular buffer
pointer has wrapped around—at which point the initialization
sequence is complete.
In FSLB configurations, a single control word per codec per
sample period is sent to the AD73322 whereas in nonFSLB, it is
possible to initialize the device in a single sample period provide
the SCLK rate is programmed to a high rate. It is also possible
to use autobuffering in which case an interrupt is generated
when the entire initialization sequence has been sent to the
AD73322.
Running the AD73322 with ADCs or DACs in Power-Down
The programmability of the AD73322 allows the user flexibility
in choosing what sections of the AD73322 need be powered up.
This allows better matching of the power consumption to the
application requirements as the AD73322 offers two ADCs and
two DACs in any combination. The AD73322 always interfaces
to the DSP in a standard way regardless of what ADC or DAC
sections are enabled or disabled. Therefore the DSP will expect
to receive two ADC samples per sample period and to transmit
two DAC samples per sample period. If a particular ADC is
disabled (in power-down) then its sample value will be invalid.
Likewise a sample sent to a DAC which is disabled will have no
effect.
There are two distinct phases of operation of the AD73322:
initialization of the device via each codec section’s control regis-
ters, and operation of the converter sections of each codec. The
initialization phase involves programming the control registers
of the AD73322 to ensure the required operating characteristics
such as sampling rate, serial clock rate, I/O gain, etc. There are
several ways in which the DSP can be programmed to initialize
the AD73322. These range from hard-coding a sequence of
DSP SPORT Tx register writes with constants used for the
initialization words, to putting the initialization sequence in a
circular data buffer and using an autobuffered transmit sequence.
Hard-coding involves creating a sequence of writes to the DSP’s
SPORT Tx buffer which are separated by loops or instructions
that idle and wait for the next Tx interrupt to occur as shown in
the code below.
ax0 = b#1000100100000100;
tx0 = ax0;
idle; {wait for tx register to send current word}
