AD73322LARUZ Datasheet AD73322LARUZ, AD73322LARUZ-REEL | P22-P24

AD73322

–21–REV. B

Table XIV. Control Register A Description

CONTROL REGISTER A

76543210

TESER2CD1CD0CDBLSBLDMM

/ATAD

MGP

Bit Name Description

0 DATA/PGM Operating Mode (0 = Program; 1 = Data Mode)

1 MM Mixed Mode (0 = Off; 1 = Enabled)

2 DLB Digital Loop-Back Mode (0 = Off; 1 = Enabled)

3 SLB SPORT Loop-Back Mode (0 = Off; 1 = Enabled)

4 DC0 Device Count (Bit 0)

5 DC1 Device Count (Bit 1)

6 DC2 Device Count (Bit 2)

7 RESET Software Reset (0 = Off; 1 = Initiates Reset)

Table XV. Control Register B Description

CONTROL REGISTER B

76 54321 0

CEE MCD2 MCD1 MCD0 SCD1 SCD0 DIR1 DIR0

Bit Name Description

0 DIR0 Decimation/Interpolation Rate (Bit 0)

1 DIR1 Decimation/Interpolation Rate (Bit 1)

2 SCD0 Serial Clock Divider (Bit 0)

3 SCD1 Serial Clock Divider (Bit 1)

4 MCD0 Master Clock Divider (Bit 0)

5 MCD1 Master Clock Divider (Bit 1)

6 MCD2 Master Clock Divider (Bit 2)

7 CEE Control Echo Enable (0 = Off; 1 = Enabled)

Table XVI. Control Register C Description

CONTROL REGISTER C

76 54321 0

5VEN RU PUREF PUDAC PUADC PUIA PUAGT PU

Bit Name Description

0 PU Power-Up Device (0 = Power-Down; 1 = Power On)

1 PUAGT Analog Gain Tap Power (0 = Power-Down; 1 = Power On)

2 PUIA Input Amplifier Power (0 = Power-Down; 1 = Power On)

3 PUADC ADC Power (0 = Power-Down; 1 = Power On)

4 PUDAC DAC Power (0 = Power-Down; 1 = Power On)

5 PUREF REF Power (0 = Power-Down; 1 = Power On)

6 RU REFOUT Use (0 = Disable REFOUT; 1 = Enable REFOUT)

7 5VEN Enable 5 V Operating Mode (0 = Disable 5 V Mode;

1 = Enable 5 V Mode)

AD73322

–22–

REV. B

Table XVII. Control Register D Description

CONTROL REGISTER D

76 543210

MUTE OGS2 OGS1 OGS0 RMOD IGS2 IGS1 IGS0

Bit Name Description

0 IGS0 Input Gain Select (Bit 0)

1 IGS1 Input Gain Select (Bit 1)

2 IGS2 Input Gain Select (Bit 2)

3 RMOD Reset ADC Modulator (0 = Off; 1 = Reset Enabled)

4 OGS0 Output Gain Select (Bit 0)

5 OGS1 Output Gain Select (Bit 1)

6 OGS2 Output Gain Select (Bit 2)

7 MUTE Output Mute (0 = Mute Off; 1 = Mute Enabled)

Table XVIII. Control Register E Description

CONTROL REGISTER E

76 54321 0

— DGTE IBYP DA4 DA3 DA2 DA1 DA0

Bit Name Description

0 DA0 DAC Advance Setting (Bit 0)

1 DA1 DAC Advance Setting (Bit 1)

2 DA2 DAC Advance Setting (Bit 2)

3 DA3 DAC Advance Setting (Bit 3)

4 DA4 DAC Advance Setting (Bit 4)

5 IBYP Interpolator Bypass (0 = Bypass Disabled; 1 = Bypass Enabled)

6 DGTE Digital Gain Tap Enable (0 = Disabled; 1 = Enabled)

7 — Reserved (Program to 0)

Table XIX. Control Register F Description

CONTROL REGISTER F

76 54321 0

ALB/

AGTM INV

SEEN/

AGTE AGTC4 AGTC3 AGTC2 AGTC1 AGTC0

Bit Name Description

0 AGTC0 Analog Gain Tap Coefficient (Bit 0)

1 AGTC1 Analog Gain Tap Coefficient (Bit 1)

2 AGTC2 Analog Gain Tap Coefficient (Bit 2)

3 AGTC3 Analog Gain Tap Coefficient (Bit 3)

4 AGTC4 Analog Gain Tap Coefficient (Bit 4)

5 SEEN/ Single-Ended Enable (0 = Disabled; 1 = Enabled)

AGTE Analog Gain Tap Enable (0 = Disabled; 1 = Enabled)

6 INV Input Invert (0 = Disabled; 1 = Enabled)

7 ALB/ Analog Loopback of Output to Input (0 = Disabled; 1 = Enabled)

AGTM Analog Gain Tap Mute (0 = Off; 1 = Muted)

AD73322

–23–REV. B

Table XX. Control Register G Description

CONTROL REGISTER G

76 54321 0

DGTC7 DGTC6 DGTC5 DGTC4 DGTC3 DGTC2 DGTC1 DGTC0

Bit Name Description

0 DGTC0 Digital Gain Tap Coefficient (Bit 0)

1 DGTC1 Digital Gain Tap Coefficient (Bit 1)

2 DGTC2 Digital Gain Tap Coefficient (Bit 2)

3 DGTC3 Digital Gain Tap Coefficient (Bit 3)

4 DGTC4 Digital Gain Tap Coefficient (Bit 4)

5 DGTC5 Digital Gain Tap Coefficient (Bit 5)

6 DGTC6 Digital Gain Tap Coefficient (Bit 6)

7 DGTC7 Digital Gain Tap Coefficient (Bit 7)

Table XXI. Control Register H Description

CONTROL REGISTER H

76 54321 0

DGTC15 DGTC14 DGTC13 DGTC12 DGTC11 DGTC10 DGTC9 DGTC8

Bit Name Description

0 DGTC8 Digital Gain Tap Coefficient (Bit 8)

1 DGTC9 Digital Gain Tap Coefficient (Bit 9)

2 DGTC10 Digital Gain Tap Coefficient (Bit 10)

3 DGTC11 Digital Gain Tap Coefficient (Bit 11)

4 DGTC12 Digital Gain Tap Coefficient (Bit 12)

5 DGTC13 Digital Gain Tap Coefficient (Bit 13)

6 DGTC14 Digital Gain Tap Coefficient (Bit 14)

7 DGTC15 Digital Gain Tap Coefficient (Bit 15)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P44

AD73322LARUZ

Mfr. #:

Buy AD73322LARUZ

Manufacturer:

Analog Devices Inc.

Description:

Analog Front End - AFE Dual-Ch 3V Front-End Processor

Lifecycle:

New from this manufacturer.

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AD73322LARUZ

AD73322LARUZ

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