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AD73322LARUZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P44
AD73322
–6–
REV. B
AD73322A
P
arameter Min Typ Max Units Test Conditions/Comments
DIGITAL GAIN TAP
Gain at Maximum Setting +1 V
Gain at Minimum Setting –1 V
Gain Resolution 16 Bits Tested to 5 MSBs of Settings
Delay 25 µs Includes DAC Delay
Settling Time 100 µs Tap Gain Change from –FS to +FS; Includes
DAC Settling Time
DAC SPECIFICATIONS 5VEN = 1
Maximum Voltage Output Swing
2
Single-Ended 3.156 V p-p PGA = 6 dB
3.17 dBm Max Output = (3.156/2.4) × VREFCAP
Differential 6.312 V p-p PGA = 6 dB
9.19 dBm Max Output = 2 × ([3.156/2.4] × VREFCAP)
Nominal Voltage Output Swing (0 dBm0)
Single-Ended 2.1908 V p-p PGA = 6 dB
0 dBm
Differential 4.3918 V p-p PGA = 6 dB
6.02 dBm
Output Bias Voltage 2.4 V REFOUT Unloaded
Absolute Gain +0.4 dB 1.0 kHz, 0 dBm0; Unloaded
Gain Tracking Error ±0.1 dB 1.0 kHz, +3 dBm0 to –50 dBm0
Signal to (Noise + Distortion) at 0 dBm0 Refer to Figure 8
PGA = 6 dB 77 dB 300 Hz to 3400 Hz; f
SAMP
= 64 kHz
Total Harmonic Distortion at 0 dBm0
PGA = 6 dB –80 dB 300 Hz to 3400 Hz; f
SAMP
= 64 kHz
Intermodulation Distortion –85 dB PGA = 0 dB
Idle Channel Noise –85 dBm0 PGA = 0 dB
Crosstalk DAC-to-ADC –90 dB ADC Input Signal Level: AGND; DAC
Output Signal Level: 1.0 kHz, 0 dBm0;
Input Amplifiers Bypassed
–77 dB Input Amplifiers Included In Input Channel
DAC-to-DAC –100 dB DAC1 Output Signal Level: AGND; DAC2
Output Signal Level: 1.0 kHz, 0 dBm0
Power Supply Rejection –65 dB Input Signal Level at AVDD and DVDD
Pins: 1.0 kHz, 100 mV p-p Sine Wave
Group Delay
4, 5
25 µs Interpolator Bypassed
50 µs
Output DC Offset
2, 7
+12 mV
Minimum Load Resistance, R
L
2, 8
Single-Ended 150 Ω
Differential 150 Ω
Maximum Load Capacitance, C
L
2, 8
Single-Ended 500 pF
Differential 100 pF
FREQUENCY RESPONSE
(ADC and DAC)
9
Typical Output
Frequency (Normalized to FS)
00dB
0.03125 –0.1 dB
0.0625 –0.25 dB
0.125 –0.6 dB
0.1875 –1.4 dB
0.25 –2.8 dB
0.3125 –4.5 dB
0.375 –7.0 dB
0.4375 –9.5 dB
> 0.5 < –12.5 dB
–7–REV. B
AD73322
AD73322A
Parameter Min Typ Max Units Test Conditions/Comments
LOGIC INPUTS
V
INH
, Input High Voltage DVDD – 0.8 DVDD V
V
INL
, Input Low Voltage 0 0.8 V
I
IH
, Input Current ±0.5 µA
C
IN
, Input Capacitance 10 pF
LOGIC OUTPUT
V
OH
, Output High Voltage DVDD – 0.4 DVDD V |I
OUT
| ≤ 100 µA
V
OL
, Output Low Voltage 0 0.4 V |I
OUT
| ≤ 100 µA
Three-State Leakage Current ±0.3 µA
POWER SUPPLIES
AVDD1, AVDD2 4.5 5.5 V
DVDD 4.5 5.5 V
I
DD
10
See Table II
NOTES
1
Operating temperature range is as follows: –40°C to +85°C. Therefore, T
MIN
= –40°C and T
MAX
= +85°C.
2
Test conditions: Input PGA set for 0 dB gain, Output PGA set for 6 dB gain, no load on analog outputs (unless otherwise stated).
3
At input to sigma-delta modulator of ADC.
4
Guaranteed by design.
5
Overall group delay will be affected by the sample rate and the external digital filtering.
6
The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (3.3 × 10
11
)/DMCLK.
7
Between VOUTP and VOUTN.
8
At VOUT output.
9
Frequency responses of ADC and DAC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB
preamplifier bypassed and input gain of 0 dB.
10
Test conditions: no load on digital inputs, analog inputs ac coupled to ground, no load on analog outputs.
Specifications subject to change without notice.
Table II. Current Summary (AVDD = DVDD = +5.5 V)
Analog Digital Total Current MCLK
Conditions Current Current (Typ) SE ON Comments
ADCs On Only 7.5 9 16.5 1 YES REFOUT Disabled
DACs On Only 16 9 25 1 YES REFOUT Disabled
ADC and DAC On 20.5 10 30.5 1 YES REFOUT Disabled
ADCs and DACs
and Input Amps On 27 10 37 1 YES REFOUT Disabled
ADCs and DACs
and AGT On 25 10 35 1 YES REFOUT Disabled
All Sections On 35 10 45 1 YES
REFCAP On Only 0.8 0 0.8 0 NO REFOUT Disabled
REFCAP and
REFOUT On Only 3.5 0 3.5 0 NO
All Sections Off 0 3 3 0 YES MCLK Active Levels Equal to 0 V and DVDD
All Sections Off 0 10 µA 10 µA 0 NO Digital Inputs Static and Equal to 0 V or DVDD
The above values are in mA and are typical values unless otherwise noted.
AD73322
–8–
REV. B
Table III. Signal Ranges
3 V Power Supply 5 V Power Supply
5VEN = 0 5VEN = 0 5VEN = 1
VREFCAP 1.2 V ± 10% 1.2 V 2.4 V
VREFOUT 1.2 V ± 10% 1.2 V 2.4 V
ADC Maximum Input Range
at V
IN
1.578 V p-p 1.578 V p-p 3.156 V p-p
Nominal Reference Level 1.0954 V p-p 1.0954 V p-p 2.1908 V p-p
DAC Maximum Voltage
Output Swing
Single-Ended 1.578 V p-p 1.578 V p-p 3.156 V p-p
Differential 3.156 V p-p 3.156 V p-p 6.312 V p-p
Nominal Voltage
Output Swing
Single-Ended 1.0954 V p-p 1.0954 V p-p 2.1908 V p-p
Differential 2.1909 V p-p 2.1909 V p-p 4.3818 V p-p
Output Bias Voltage VREFOUT VREFOUT VREFOUT
TIMING CHARACTERISTICS
Limit at
Parameter T
A
= –40ⴗC to +85ⴗC Units Description
Clock Signals See Figure 1
t
1
61 ns min MCLK Period
t
2
24.4 ns min MCLK Width High
t
3
24.4 ns min MCLK Width Low
Serial Port See Figures 3 and 4
t
4
t
1
ns min SCLK Period
t
5
0.4 × t
1
ns min SCLK Width High
t
6
0.4 × t
1
ns min SCLK Width Low
t
7
20 ns min SDI/SDIFS Setup Before SCLK Low
t
8
0 ns min SDI/SDIFS Hold After SCLK Low
t
9
10 ns max SDOFS Delay from SCLK High
t
10
10 ns min SDOFS Hold After SCLK High
t
11
10 ns min SDO Hold After SCLK High
t
12
10 ns max SDO Delay from SCLK High
t
13
30 ns max SCLK Delay from MCLK
Specifications subject to change without notice.
(AVDD = +3 V ⴞ 10%; DVDD = +3 V ⴞ 10%; AGND = DGND = 0 V; T
A
= T
MlN
to T
MAX
, unless
otherwise noted)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P44

AD73322LARUZ

Mfr. #:
Buy AD73322LARUZ
Manufacturer:
Analog Devices Inc.
Description:
Analog Front End - AFE Dual-Ch 3V Front-End Processor
Lifecycle:
New from this manufacturer.
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