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AD73322LARUZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P44
–3–REV. B
AD73322
AD73322A
Parameter Min Typ Max Units Test Conditions/Comments
DAC SPECIFICATIONS 5VEN = 0
Maximum Voltage Output Swing
2
Single-Ended 1.578 V p-p PGA = 6 dB
–2.85 dBm Max Output = (1.578/1.2) × VREFCAP
Differential 3.156 V p-p PGA = 6 dB
3.17 dBm Max Output = 2 × ([1.578/1.2] × VREFCAP)
Nominal Voltage Output Swing (0 dBm0)
Single-Ended 1.0954 V p-p PGA = 6 dB
–6.02 dBm
Differential 2.1909 V p-p PGA = 6 dB
0 dBm
Output Bias Voltage 1.2 V REFOUT Unloaded
Absolute Gain –0.8 +0.4 +1.2 dB 1.0 kHz, 0 dBm0; Unloaded
Gain Tracking Error ±0.1 dB 1.0 kHz, +3 dBm0 to –50 dBm0
Signal to (Noise + Distortion) at 0 dBm0 Refer to Figure 6; AVDD = 3.0 V ± 5%
PGA = 6 dB 62.5 77 dB 300 Hz to 3400 Hz; f
SAMP
= 64 kHz
Total Harmonic Distortion at 0 dBm0 AVDD = 3.00 V ± 5%
PGA = 6 dB –80 –62.5 dB 300 Hz to 3400 Hz; f
SAMP
= 64 kHz
Intermodulation Distortion –85 dB PGA = 0 dB
Idle Channel Noise –85 dBm0 PGA = 0 dB
Crosstalk DAC-to-ADC –90 dB ADC Input Signal Level: AGND; DAC
Output Signal Level: 1.0 kHz, 0 dBm0
Input Amplifiers Bypassed
–77 dB Input Amplifiers Included in Input Channel
DAC-to-DAC –100 dB DAC1 Output Signal Level: AGND; DAC2
Output Signal Level: 1.0 kHz, 0 dBm0
Power Supply Rejection –65 dB Input Signal Level at AVDD and DVDD
Pins: 1.0 kHz, 100 mV p-p Sine Wave
Group Delay
4, 5
25 µs Interpolator Bypassed
50 µs
Output DC Offset
2, 7
–25 +12 +40 mV
Minimum Load Resistance, R
L
2, 8
Single-Ended
4
150 Ω
Differential 150 Ω
Maximum Load Capacitance, C
L
2, 8
Single-Ended 500 pF
Differential 100 pF
FREQUENCY RESPONSE
(ADC and DAC)
9
Typical Output
Frequency (Normalized to FS)
00dB
0.03125 –0.1 dB
0.0625 –0.25 dB
0.125 –0.6 dB
0.1875 –1.4 dB
0.25 –2.8 dB
0.3125 –4.5 dB
0.375 –7.0 dB
0.4375 –9.5 dB
> 0.5 < –12.5 dB
AD73322
–4–
REV. B
Table I. Current Summary (AVDD = DVDD = +3.3 V)
Analog Digital Total Current Total Current MCLK
Conditions Current Current (Typ) (Max) SE ON Comments
ADCs On Only 7 4.5 11.5 13 1 YES REFOUT Disabled
DACs On Only 15.5 4.5 20 23 1 YES REFOUT Disabled
ADCs and DACs On 19.5 5 24.5 28 1 YES REFOUT Disabled
ADCs and DACs
and Input Amps On 25 5 30 34 1 YES REFOUT Disabled
ADCs and DACs
and AGT On 24 5 29 32.5 1 YES REFOUT Disabled
All Sections On 32 5 37 42 1 YES
REFCAP On Only 0.8 0 0.8 1.25 0 NO REFOUT Disabled
REFCAP and
REFOUT On Only 3.5 0 3.5 4.5 0 NO
All Sections Off 0 1.5 1.5 1.9 0 YES MCLK Active Levels Equal to
0 V and DVDD
All Sections Off 0.00 10 µA 10 µA 40 µA 0 NO Digital Inputs Static and Equal
to 0 V or DVDD
The above values are in mA and are typical values unless otherwise noted.
AD73322A
Parameter Min Typ Max Units Test Conditions/Comments
LOGIC INPUTS
V
INH
, Input High Voltage DVDD – 0.8 DVDD V
V
INL
, Input Low Voltage 0 0.8 V
I
IH
, Input Current –10 +10 µA
C
IN
, Input Capacitance 10 pF
LOGIC OUTPUT
V
OH
, Output High Voltage DVDD – 0.4 DVDD V |IOUT| ≤ 100 µA
V
OL
, Output Low Voltage 0 0.4 V |IOUT| ≤ 100 µA
Three-State Leakage Current –10 +10 µA
POWER SUPPLIES
AVDD1, AVDD2 2.7 3.3 V
DVDD 2.7 3.3 V
I
DD
10
See Table I
NOTES
1
Operating temperature range is as follows: –40°C to +85°C. Therefore, T
MIN
= –40°C and T
MAX
= +85°C.
2
Test conditions: Input PGA set for 0 dB gain, Output PGA set for 6 dB gain, no load on analog outputs (unless otherwise noted).
3
At input to sigma-delta modulator of ADC.
4
Guaranteed by design.
5
Overall group delay will be affected by the sample rate and the external digital filtering.
6
The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (3.3 × 10
11
)/DMCLK.
7
Between VOUTP1 and VOUTN1 or between VOUTP2 and VOUTN2.
8
At VOUT output.
9
Frequency responses of ADC and DAC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB pream-
plifier bypassed and input gain of 0 dB.
10
Test Conditions: no load on digital inputs, analog inputs ac coupled to ground, no load on analog outputs.
Specifications subject to change without notice.
–5–REV. B
AD73322
SPECIFICATIONS
1
AD73322A
Parameter Min Typ Max Units Test Conditions/Comments
REFERENCE
REFCAP
Absolute Voltage, VREFCAP 1.2 V 5VEN = 0
2.4 V 5VEN = 1
REFCAP TC 50 ppm/°C 0.1 µF Capacitor Required from
REFOUT REFCAP to AGND2
Typical Output Impedance 130 Ω
Absolute Voltage, VREFOUT 1.2 V 5VEN = 0, Unloaded
2.4 V 5VEN = 1, Unloaded
Minimum Load Resistance 2 kΩ 5VEN = 1
Maximum Load Capacitance 100 pF
INPUT AMPLIFIER
Offset ±1.0 mV
Maximum Output Swing 3.156 V Max Output Swing = (3.156/2.4) × VREFCAP
Feedback Resistance 50 kΩ f
C
= 32 kHz
Feedback Capacitance 100 pF
ANALOG GAIN TAP
Gain at Maximum Setting +1
Gain at Minimum Setting –1
Gain Resolution 5 Bits Gain Step Size = 0.0625
Gain Accuracy ±1 % Output Unloaded
Settling Time 1.0 µs Tap Gain Change of –FS to +FS
Delay 0.5 µs
ADC SPECIFICATIONS 5VEN = 1
Maximum Input Range at VIN
2, 3
3.156 V p-p Measured Differentially
3.17 dBm Max Input Swing = (3.156/2.4) × VREFCAP
Nominal Reference Level at VIN 2.1908 V p-p Measured Differentially
(0 dBm0) 0 dBm
Absolute Gain
PGA = 0 dB 0.4 dB 1.0 kHz, 0 dBm0
PGA = 38 dB –0.7 dB 1.0 kHz, 0 dBm0
Gain Tracking Error ±0.1 dB 1.0 kHz, +3 dBm0 to –50 dBm0
Signal to (Noise + Distortion) Refer to Figure 7
PGA = 0 dB 78 dB 300 Hz to 3400 Hz; f
SAMP
= 64 kHz
78 dB 300 Hz to 3400 Hz; f
SAMP
= 8 kHz
57 dB 0 Hz to f
SAMP
/2; f
SAMP
= 64 kHz
PGA = 38 dB 56 dB 300 Hz to 3400 Hz; f
SAMP
= 64 kHz
Total Harmonic Distortion
PGA = 0 dB –84 dB 300 Hz to 3400 Hz; f
SAMP
= 64 kHz
PGA = 38 dB –70 dB 300 Hz to 3400 Hz; f
SAMP
= 64 kHz
Intermodulation Distortion –65 dB PGA = 0 dB
Idle Channel Noise –71 dBm0 PGA = 0 dB
Crosstalk ADC-to-DAC –100 dB ADC Input Signal Level: 1.0 kHz, 0 dBm0
DAC Input at Idle
ADC-to-ADC –100 dB ADC1 Input Signal Level: 1.0 kHz, 0 dBm0
ADC2 Input at Idle. Input Amplifiers Bypassed
–70 dB Input Amplifiers Included in Channel
DC Offset +10 mV PGA = 0 dB
Power Supply Rejection –65 dB Input Signal Level at AVDD and DVDD
Pins: 1.0 kHz, 100 mV p-p Sine Wave
Group Delay
4, 5
25 µs 64 kHz Output Sample Rate
Input Resistance at PGA
2,
4, 6
20 kΩ Input Amplifiers Bypassed
(AVDD = +5 V ⴞ 10%; DVDD = +5 V ⴞ 10%; DGND = AGND = 0 V, f
DMCLK
= 16.384 MHz, f
SAMP
= 64 kHz;
T
A
= T
MIN
to T
MAX
, unless otherwise noted)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P44

AD73322LARUZ

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Buy AD73322LARUZ
Manufacturer:
Analog Devices Inc.
Description:
Analog Front End - AFE Dual-Ch 3V Front-End Processor
Lifecycle:
New from this manufacturer.
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