AD73322
–18–
REV. B
Table VI. Analog Gain Tap Settings*
AGTC4 AGTC3 AGTC2 AGTC1 AGTC0 Gain (dB)
0 0 0 0 0 +1.00
0 0 0 0 1 +0.9375
0 0 0 1 0 +0.875
0 0 0 1 1 +0.8125
0 0 1 0 0 +0.75
–––– ––
0 1 1 1 1 +0.0625
1 0 0 0 0 –0.0625
–––– ––
1 1 1 0 1 –0.875
1 1 1 1 0 –0.9375
1 1 1 1 1 –1.00
*AGT and DGT weights are given for the case of VFBNx (connected to the
sigma-delta modulator’s positive input) being at a higher potential than VFBPx
(connected to the sigma-delta modulator’s negative input).
Digital Gain Tap
The digital gain tap features a programmable gain block whose
input is taken from the bitstream output of the ADC’s sigma-
delta modulator. This single bit input (1 or 0) is used to add or
subtract a programmable value, which is the digital gain tap setting,
to the output of the DAC section’s interpolator. The program-
mable setting has 16-bit resolution and is programmed using the
settings in Control Registers G and H. (See Table VII).
Table VII. Digital Gain Tap Settings*
DGT15–0 (Hex) Gain
0x8000 –1.00
0x9000 –0.875
0xA000 –0.75
0xC000 –0.5
0xE000 –0.25
0x0000 0.00
0x2000 +0.25
0x4000 +0.05
0x6000 +0.75
0x7FFF +0.99999
*AGT and DGT weights are given for the case of VFBNx (connected to the
sigma-delta modulator’s positive input) being at a higher potential than VFBPx
(connected to the sigma-delta modulator’s negative input).
Serial Port (SPORT)
The codecs communicate with a host processor via the bidirec-
tional synchronous serial port (SPORT), which is compatible
with most modern DSPs. The SPORT is used to transmit and
receive digital data and control information. The dual codec is
implemented using two separate codec blocks that are internally
cascaded with serial port access to the input of Codec1 and the
output of Codec2. This allows other single or dual codec de-
vices to be cascaded together (up to a limit of eight codec units).
In both transmit and receive modes, data is transferred at the
serial clock (SCLK) rate with the MSB being transferred first.
Due to the fact that the SPORT of each codec block uses a com-
mon serial register for serial input and output, communications
between an AD73322 codec and a host processor (DSP engine)
must always be initiated by the codecs themselves. In this con-
figuration the codecs are described as being in Master mode.
This ensures that there is no collision between input data and
output samples.
SPORT Overview
The AD73322 SPORT is a flexible, full-duplex, synchronous
serial port whose protocol has been designed to allow up to four
AD73322 devices (or combinations of AD73322 dual codecs
and AD73311 single codecs up to eight codec blocks) to be con-
nected, in cascade, to a single DSP via a six-wire interface. It has a
very flexible architecture that can be configured by programming
two of the internal control registers in each codec block. The
AD73322 SPORT has three distinct modes of operation: Control
Mode, Data Mode and Mixed Control/Data Mode.
NOTE: As each codec has its own SPORT section, the register
settings in both SPORTs must be programmed. The registers
that control SPORT and sample rate operation (CRA and CRB)
must be programmed with the same values, otherwise incorrect
operation may occur.
In Control Mode (CRA:0 = 0), the device’s internal configura-
tion can be programmed by writing to the eight internal control
registers. In this mode, control information can be written to or
read from the codec. In Data Mode (CRA:0 = 1), (CRA:1 = 0),
information sent to the device is used to update the decoder
section (DAC), while the encoder section (ADC) data is read
from the device. In this mode, only DAC and ADC data is
written to or read from the device. Mixed mode (CRA:0 = 1
and CRA:1 = 1) allows the user to choose whether the informa-
tion being sent to the device contains either control information
or DAC data. This is achieved by using the MSB of the 16-bit
frame as a flag bit. Mixed mode reduces the resolution to 15 bits
with the MSB being used to indicate whether the information in
the 16-bit frame is control information or DAC/ADC data.
The SPORT features a single 16-bit serial register that is used
for both input and output data transfers. As the input and out-
put data must share the same register, some precautions must be
observed. The primary precaution is that no information must
be written to the SPORT without reference to an output sample
event, which is when the serial register will be overwritten with
the latest ADC sample word. Once the SPORT starts to output
the latest ADC word, it is safe for the DSP to write new control
or data words to the codec. In certain configurations, data can
be written to the device to coincide with the output sample
being shifted out of the serial register—see section on interfac-
ing devices. The serial clock rate (CRB:2–3) defines how many
16-bit words can be written to a device before the next output
sample event will happen.
The SPORT block diagram shown in Figure 14 details the
blocks associated with Codecs 1 and 2, including the eight
control registers (A–H), external MCLK to internal DMCLK
divider and serial clock divider. The divider rates are controlled
by the setting of Control Register B. The AD73322 features a
master clock divider that allows users the flexibility of dividing
externally available high frequency DSP or CPU clocks to gen-
erate a lower frequency master clock internally in the codec,
which may be more suitable for either serial transfer or sampling
rate requirements. The master clock divider has five divider
options (÷1 default condition, ÷2, ÷3, ÷4, ÷5) that are set by
loading the master clock divider field in Register B with the
appropriate code (see Table VIII). Once the internal device master
clock (DMCLK) has been set using the master clock divider, the
sample rate and serial clock settings are derived from DMCLK.
