AD73322
–12–
REV. B
TERMINOLOGY
Absolute Gain
Absolute gain is a measure of converter gain for a known signal.
Absolute gain is measured (differentially) with a 1 kHz sine
wave at 0 dBm0 for the DAC and with a 1 kHz sine wave at
0 dBm0 for the ADC. The absolute gain specification is used for
gain tracking error specification.
Crosstalk
Crosstalk is due to coupling of signals from a given channel to
an adjacent channel. It is defined as the ratio of the amplitude of
the coupled signal to the amplitude of the input signal. Crosstalk
is expressed in dB.
Gain Tracking Error
Gain tracking error measures changes in converter output for
different signal levels relative to an absolute signal level. The
absolute signal level is 0 dBm0 (equal to absolute gain) at 1 kHz
for the DAC and 0 dBm0 (equal to absolute gain) at 1 kHz for
the ADC. Gain tracking error at 0 dBm0 (ADC) and 0 dBm0
(DAC) is 0 dB by definition.
Group Delay
Group Delay is defined as the derivative of radian phase with
respect to radian frequency, dø(f)/df. Group delay is a measure
of average delay of a system as a function of frequency. A linear
system with a constant group delay has a linear phase response.
The deviation of group delay from a constant indicates the
degree of nonlinear phase response of the system.
Idle Channel Noise
Idle channel noise is defined as the total signal energy measured
at the output of the device when the input is grounded (mea-
sured in the frequency range 300 Hz–3400 Hz).
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n is equal to zero. For final testing, the second
order terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
Power Supply Rejection
Power supply rejection measures the susceptibility of a device to
noise on the power supply. Power supply rejection is measured
by modulating the power supply with a sine wave and measuring
the noise at the output (relative to 0 dB).
Sample Rate
The sample rate is the rate at which the ADC updates its output
register and the DAC updates its output from its input register.
The sample rate can be chosen from a list of four that are fixed
relative to the DMCLK. Sample rate is set by programming bits
DIR0-1 in Control Register B of each channel.
SNR+THD
Signal-to-noise ratio plus total harmonic distortion is defined to
be the ratio of the rms value of the measured input signal to the
rms sum of all other spectral components in the frequency range
300 Hz–3400 Hz, including harmonics but excluding dc.
ABBREVIATIONS
ADC Analog-to-Digital Converter.
AFE Analog Front End.
AGT Analog Gain Tap.
ALB Analog Loop-Back.
BW Bandwidth.
CRx A Control Register where x is a placeholder for an
alphabetic character (A–E). There are five read/
write control registers on the AD73322—desig-
nated CRA through CRE.
CRx:n A bit position, where n is a placeholder for a nu-
meric character (0–7), within a control register,
where x is a placeholder for an alphabetic charac-
ter (A–E). Position 7 represents the MSB and
Position 0 represents the LSB.
DAC Digital-to-Analog Converter.
DGT Digital Gain Tap.
DLB Digital Loop-Back.
DMCLK Device (Internal) Master Clock. This is the inter-
nal master clock resulting from the external master
clock (MCLK) being divided by the on-chip mas-
ter clock divider.
FS Full Scale.
FSLB Frame Sync Loop-Back—where the SDOFS of
the final device in a cascade is connected to the
RFS and TFS of the DSP and the SDIFS of
first device in the cascade. Data input and out-
put occur simultaneously. In the case of Non-
FSLB, SDOFS and SDO are connected to the
Rx Port of the DSP while SDIFS and SDI are
connected to the Tx Port.
PGA Programmable Gain Amplifier.
SC Switched Capacitor.
SLB Sport Loop-Back
SNR Signal-to-Noise Ratio.
SPORT Serial Port.
THD Total Harmonic Distortion.
VBW Voice Bandwidth.
AD73322
–13–REV. B
V
IN
dBm0
–85 5–75 –65 –55 –45 –35 –25 –15 –5
80
70
–10
S/(N+D) – dB
30
20
10
0
50
40
60
3.17
Figure 5. S/(N+D) vs. V
IN
(ADC @ 3 V) over Voiceband
Bandwidth (300 Hz–3.4 kHz)
V
IN
dBm0
–85 5–75 –65 –55 –45 –35 –25 –15 –5
80
70
–10
S/(N+D) – dB
30
20
10
0
50
40
60
3.17
Figure 6. S/(N+D) vs. V
IN
(DAC @ 3 V) over Voiceband
Bandwidth (300 Hz–3.4 kHz)
V
IN
dBm0
–85 5–75 –65 –55 –45 –35 –25 –15 –5
80
70
–10
S/(N+D) – dB
30
20
10
0
50
40
60
3.17
Figure 7. S/(N+D) vs. V
IN
(ADC @ 5 V) over Voiceband
Bandwidth (300 Hz–3.4 kHz)
V
IN
dBm0
–85 5–75 –65 –55 –45 –35 –25 –15 –5
80
70
–10
S/(N+D) – dB
30
20
10
0
50
40
60
3.17
Figure 8. S/(N+D) vs. V
IN
(DAC @ 5 V) over Voiceband
Bandwidth (300 Hz–3.4 kHz)
Typical Performance Characteristics
AD73322
–14–
REV. B
GAIN
61
INVERT
SINGLE-ENDED
ENABLE
0/38dB
PGA
DECIMATOR
SERIAL
I/O
PORT
+6/–15dB
PGA
CONTINUOUS
TIME
LOW-PASS
FILTER
1-BIT
DAC
SWITCHED
CAPACITOR
LOW-PASS
FILTER
DIGITAL
SIGMA-
DELTA
MODULATOR
GAIN
61
INTER-
POLATOR
V
REF
VFBN1
VINN1
VINP1
VFBP1
VOUTP1
VOUTN1
REFCAP
REFOUT
DECIMATOR
+6/–15dB
CONTINUOUS
TIME
LOW-PASS
FILTER
1-BIT
DAC
SWITCHED
CAPACITOR
LOW-PASS
FILTER
DIGITAL
SIGMA-
DELTA
MODULATOR
GAIN
61
INTER-
POLATOR
V
REF
VFBN2
VINN2
VINP2
VFBP2
VOUTP2
VOUTN2
AD73322
AGND1 AGND2 DGND
SDOFS
SDO
MCLK
SE
RESET
SCLK
SDIFS
SDI
DVDDAVDD2AVDD1
REFERENCE
PGA
ANALOG
SIGMA-DELTA
MODULATOR
ANALOG
LOOP
BACK
GAIN
61
INVERT
SINGLE-ENDED
ENABLE
0/38dB
PGA
ANALOG
SIGMA-DELTA
MODULATOR
ANALOG
LOOP
BACK
Figure 9. Functional Block Diagram
FUNCTIONAL DESCRIPTION
Encoder Channels
Both encoder channels consist of a pair of inverting op amps
with feedback connections that can be bypassed if required, a
switched capacitor PGA and a sigma-delta analog-to-digital
converter (ADC). An on-board digital filter, which forms part of
the sigma-delta ADC, also performs critical system-level filter-
ing. Due to the high level of oversampling, the input antialias
requirements are reduced such that a simple single pole RC
stage is sufficient to give adequate attenuation in the band of
interest.
Programmable Gain Amplifier
Each encoder section’s analog front end comprises a switched
capacitor PGA, which also forms part of the sigma-delta modu-
lator. The SC sampling frequency is DMCLK/8. The PGA,
whose programmable gain settings are shown in Table IV, may
be used to increase the signal level applied to the ADC from low
output sources such as microphones, and can be used to avoid
placing external amplifiers in the circuit. The input signal level
to the sigma-delta modulator should not exceed the maximum
input voltage permitted.
The PGA gain is set by bits IGS0, IGS1 and IGS2 (CRD:0–2)
in control register D.
Table IV. PGA Settings for the Encoder Channel
IGS2 IGS1 IGS0 Gain (dB)
00 00
00 16
01 012
01 118
10 020
10 126
11 032
11 138

AD73322LARUZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog Front End - AFE Dual-Ch 3V Front-End Processor
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet