P89LPC9102_9103_9107_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 10 July 2007 10 of 61
NXP Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
7.2 Pin description
Table 4. P89LPC9102 pin description
Symbol Pin Type Description
P0.1 to P0.5,
P0.7
I/O Port 0: Port 0 is an I/O port with a user-configurable output type. During reset Port 0
latches are configured in the input-only mode with the internal pull-up disabled. The
operation of Port 0 pins as inputs and outputs depends upon the port configuration
selected. Each port pin is configured independently. Refer to
Section 8.12.1 “Port
configurations” and Table 12 “Static characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below:
P0.1/KBI1/
AD10
4 I/O P0.1 — Port 0 bit 1.
I KBI1 — Keyboard input 1.
I AD10 — ADC1 channel 0 analog input.
P0.2/KBI2/
AD11
1 I/O P0.2 — Port 0 bit 2.
I KBI2 — Keyboard input 2.
I AD11 — ADC1 channel 1 analog input.
P0.3/CIN1B/
AD12
10 I/O P0.3 — Port 0 bit 3.
I CIN1B — Comparator 1 positive input.
I AD12 — ADC1 channel 2 analog input.
P0.4/CIN1A/
AD13/DAC1
9 I/O P0.4 — Port 0 bit 4.
I CIN1A — Comparator 1 positive input.
I AD13 — ADC1 channel 3 analog input.
O DAC1 — Digital to analog converter output.
P0.5/CMPRE
F/CLKIN
8 I/O P0.5 — Port 0 bit 5.
I CMPREF — Comparator reference (negative) input.
I CLKIN — External clock input.
P0.7/T1/
CLKOUT
6 I/O P0.7 — Port 0 bit 7.
I/O T1 — Timer/counter 1 external count input or overflow/PWM output.
I CLKOUT — Clock output.
P1.2, P1.5 I/O Port 1: Port 1 is an I/O port with a user-configurable output type. During reset Port 1
latches are configured in the input-only mode with the internal pull-up disabled. The
operation of the configurable Port 1 pins as inputs and outputs depends upon the
port configuration selected. Each of the configurable port pins are programmed
independently. Refer to
Section 8.12.1 “Port configurations” and Table 12 “Static
characteristics” for details. P1.5 is input-only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below:
P1.2/T0 5 I/O P1.2 — Port 1 bit 2.
I/O T0 — Timer/counter 0 external count input or overflow/PWM output.
P89LPC9102_9103_9107_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 10 July 2007 11 of 61
NXP Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
P1.5/RST 2 I P1.5 — Port 1 bit 5 (input-only).
I
RST — External Reset input during power-on or if selected via User Configuration
Register 1 (UCFG1). When functioning as a reset input a LOW on this pin resets the
microcontroller, causing I/O ports and peripherals to take on their default states, and
the processor begins execution at address 0. When using an oscillator frequency
above 12 MHz, the reset input function of P1.5 must be enabled. An external
circuit is required to hold the device in reset at power-up until V
DD
has reached
its specified level. When system power is removed V
DD
will fall below the
minimum specified operating voltage. When using an oscillator frequency
above 12 MHz, in some applications, an external brownout detect circuit may
be required to hold the device in reset when V
DD
falls below the minimum
specified operating voltage.
V
SS
3IGround: 0 V reference.
V
DD
7IPower supply: This is the power supply voltage for normal operation as well as Idle
mode and Power-down mode.
Table 4. P89LPC9102 pin description
…continued
Symbol Pin Type Description
P89LPC9102_9103_9107_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 10 July 2007 12 of 61
NXP Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
Table 5. P89LPC9103 pin description
Symbol Pin Type Description
P0.1 to P0.5 I/O Port 0: Port 0 is an I/O port with a user-configurable output type. During reset Port 0
latches are configured in the input-only mode with the internal pull-up disabled. The
operation of Port 0 pins as inputs and outputs depends upon the port configuration
selected. Each port pin is configured independently. Refer to
Section 8.12.1 “Port
configurations” and Table 12 “Static characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below:
P0.1/KBI1/
AD10
4 I/O P0.1 — Port 0 bit 1.
I KBI1 — Keyboard input 1.
I AD10 — ADC1 channel 0 analog input.
P0.2/KBI2/
AD11
1 I/O P0.2 — Port 0 bit 2.
I KBI2 — Keyboard input 2.
I AD11 — ADC1 channel 1 analog input.
P0.3/CIN1B/
AD12
10 I/O P0.3 — Port 0 bit 3.
I CIN1B — Comparator 1 positive input.
I AD12 — ADC1 channel 2 analog input.
P0.4/CIN1A/
AD13/DAC1
9 I/O P0.4 — Port 0 bit 4.
I CIN1A — Comparator 1 positive input.
I AD13 — ADC1 channel 3 analog input.
O DAC1 — Digital to analog converter output.
P0.5/CMPREF/
CLKIN
6 I/O P0.5 — Port 0 bit 5.
I CMPREF — Comparator reference (negative) input.
I CLKIN — External clock input.
P1.0 to P1.5 I/O Port 1: Port 1 is an I/O port with a user-configurable output type. During reset Port 1
latches are configured in the input-only mode with the internal pull-up disabled. The
operation of the configurable Port 1 pins as inputs and outputs depends upon the port
configuration selected. Each of the configurable port pins are programmed
independently. Refer to
Section 8.12.1 “Port configurations” and Table 12 “Static
characteristics” for details. P1.5 is input-only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below:
P1.0/TXD 5 I/O P1.0 — Port 1 bit 0.
O TXD — Serial port transmitter data.
P1.1/RXD 6 I/O P1.1 — Port 1 bit 1.
I RXD — Serial port receiver data.

P89LPC9103FTK,115

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT 1KB FLASH 10HVSON
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