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P89LPC9103FTK,115

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P61
P89LPC9102_9103_9107_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 10 July 2007 49 of 61
NXP Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
[1] Typical ratings are not guaranteed. The values listed are at room temperature, 3 V.
[2] The I
DD(oper)
,I
DD(idle)
, and I
DD(pd)
specifications are measured using an external clock with the following functions disabled: comparators,
real-time clock, and watchdog timer.
[3] The I
DD(oper)
and I
DD(idle)
specifications are measured using with the following functions disabled: comparators, real-time clock, and
watchdog timer.
[4] The I
DD(tpd)
specification is measured using an external clock with the following functions disabled: comparators, real-time clock,
brownout detect, and watchdog timer.
[5] Applies to all ports, in all modes except Hi-Z.
[6] Pin capacitance is characterized but not tested.
[7] Measured with port in quasi-bidirectional mode.
[8] Measured with port in high-impedance mode.
[9] Ports in quasi-bidirectional mode with weak pull-up (applies to all port pins with pull-ups)
[10] Port pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is
highest when V
I
is approximately 2 V.
V
bo
brownout trip voltage 2.4 V < V
DD
< 3.6 V; with
BOV = 1, BOPD = 0
2.40 - 2.70 V
V
ref(bg)
band gap reference voltage 1.19 1.23 1.27 V
TC
bg
band gap temperature
coefficient
- 10 20 ppm/°C
Table 12. Static characteristics
…continued
V
DD
= 2.4 V to 3.6 V unless otherwise specified.
T
amb
=
−
40
°
C to +85
°
C for industrial applications, unless otherwise specified.
Symbol Parameter Conditions Min Typ
[1]
Max Unit
P89LPC9102_9103_9107_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 10 July 2007 50 of 61
NXP Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
12. Dynamic characteristics
[1] Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to
operate down to 0 Hz.
Table 13. Dynamic characteristics (12 MHz)
V
DD
= 2.4 V to 3.6 V unless otherwise specified.
T
amb
=
−
40
°
C to +85
°
C for industrial applications, unless otherwise specified.
[1]
Symbol Parameter Conditions Variable clock f
ext
=12MHz Unit
Min Max Min Max
f
osc(RC)
internal RC oscillator
frequency
clock doubler
option = OFF (default);
nominal f = 7.3728 MHz;
trimmed to ±1 % at
T
amb
=25°C
7.189 7.557 7.189 7.557 MHz
clock doubler
option = ON; nominal
f = 14.7456 MHz;
V
DD
= 2.7 V to 3.6 V
14.378 15.114 14.378 15.114 MHz
f
osc(WD)
internal watchdog
oscillator frequency
nominal f = 400 kHz 320 520 320 520 kHz
T
cy(clk)
clock cycle time see Figure 20 83 - - - ns
f
CLKLP
low-power select clock
frequency
0 8 - - MHz
External clock
f
ext
external clock
frequency
- - 0 12 MHz
t
CHCX
clock HIGH time V
DD
= 2.7 V to 3.6 V; see
Figure 20
33 T
cy(clk)
− t
CLCX
33 - ns
t
CLCX
clock LOW time 33 T
cy(clk)
− t
CHCX
33 - ns
t
CLCH
clock rise time - 8 - 8 ns
t
CHCL
clock fall time - 8 - 8 ns
Glitch filter
t
gr
glitch rejection P1.5/RST pin - 50 - 50 ns
any pin except P1.5/
RST - 15 - 15 ns
t
sa
signal acceptance P1.5/RST pin 125 - 125 - ns
any pin except P1.5/
RST 50 - 50 - ns
Shift register (UART mode 0 - P89LPC9103)
T
XLXL
serial port clock cycle
time
see Figure 19 16T
cy(clk)
- 1333 - ns
t
QVXH
output data set-up to
clock rising edge
see Figure 19 13T
cy(clk)
- 1083 - ns
t
XHQX
output data hold after
clock rising edge
see Figure 19 -T
cy(clk)
+ 20 - 103 ns
t
XHDX
input data hold after
clock rising edge
see Figure 19 -0-0ns
t
XHDV
input data valid to clock
rising edge
see Figure 19 150 - 150 - ns
P89LPC9102_9103_9107_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 10 July 2007 51 of 61
NXP Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
[1] Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to
operate down to 0 Hz.
Table 14. Dynamic characteristics (18 MHz)
V
DD
= 3.0 V to 3.6 V unless otherwise specified.
T
amb
=
−
40
°
C to +85
°
C for industrial applications, unless otherwise specified.
[1]
Symbol Parameter Conditions Variable clock f
ext
= 18 MHz Unit
Min Max Min Max
f
osc(RC)
internal RC oscillator
frequency
clock doubler
option = OFF (default);
nominal f = 7.3728 MHz;
trimmed to ±1 % at
T
amb
=25°C
7.189 7.557 7.189 7.557 MHz
clock doubler
option = ON; nominal
f = 14.7456 MHz
14.378 15.114 14.378 15.114 MHz
f
osc(WD)
internal watchdog
oscillator frequency
nominal f = 400 kHz 320 520 320 520 kHz
T
cy(clk)
clock cycle time see Figure 20 83 - - - ns
f
CLKLP
low-power select clock
frequency
0 8 - - MHz
External clock
f
ext
external clock
frequency
- - 0 18 MHz
t
CHCX
clock HIGH time see Figure 20 22 T
cy(clk)
− t
CLCX
22 - ns
t
CLCX
clock LOW time 22 T
cy(clk)
− t
CHCX
22 - ns
t
CLCH
clock rise time - 5 - 5 ns
t
CHCL
clock fall time - 5 - 5 ns
Glitch filter
t
gr
glitch rejection P1.5/RST pin - 50 - 50 ns
any pin except P1.5/
RST - 15 - 15 ns
t
sa
signal acceptance P1.5/RST pin 125 - 125 - ns
any pin except P1.5/
RST 50 - 50 - ns
Shift register (UART mode 0 - P89LPC9103)
T
XLXL
serial port clock cycle
time
see Figure 19 16T
cy(clk)
- 888 - ns
t
QVXH
output data set-up to
clock rising edge
see Figure 19 13T
cy(clk)
- 722 - ns
t
XHQX
output data hold after
clock rising edge
see Figure 19 -T
cy(clk)
+ 20 - 75 ns
t
XHDX
input data hold after
clock rising edge
see Figure 19 -0-0ns
t
XHDV
input data valid to clock
rising edge
see Figure 19 150 - 150 - ns
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P89LPC9103FTK,115

Mfr. #:
Buy P89LPC9103FTK,115
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT 1KB FLASH 10HVSON
Lifecycle:
New from this manufacturer.
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